2D Stacked Channel GAA Transistor for Short-Channel Gate Control
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Solution Overview
Problem
The challenge lies in developing a semiconductor device that effectively utilizes two-dimensional (2D) semiconductor materials to enhance gate control and reduce channel length, while overcoming the limitations of silicon semiconductors and achieving improved integration density in integrated circuit devices.
Innovation Solution
The semiconductor device incorporates a structure with first and second channel layers made of 2D semiconductor materials, spaced apart to allow for simultaneous contact with source and drain electrodes. This configuration includes a gate electrode and gate insulating layer within an internal space surrounded by the channel layers and electrodes, effectively creating a gate-all-around (GAA) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If silicon semiconductors are physically reduced in gate length, then integration density is improved, but manufacturing precision deteriorates due to reaching physical limitations
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional stacked channel structures, where multiple channel layers are vertically stacked to increase the effective channel width without increasing the footprint area. This dimensional change allows continued scaling and integration density improvement while avoiding the physical limitations of further reducing individual gate lengths in silicon-based planar devices.
2Length of moving object
If channel length is reduced to improve integration density, then device size is reduced, but gate control deteriorates
Solution Approach 1:
The patent implements gate-all-around (GAA) structures where gate electrodes completely surround each channel layer in three dimensions, providing 360-degree gate control. The gate electrodes are positioned above, below, and on the sides of the channel layers, creating a nested configuration that maximizes electrostatic control over the channel, thereby maintaining reliable gate control even as channel lengths are reduced for higher integration density.
3Volume of moving object
If layers are thinned to reduce device size, then integration density is improved, but electrical performance deteriorates due to reduced mobility
Solution Approach 1:
The patent employs composite material structures combining multiple thin semiconductor layers (such as SiGe/Si/SiGe heterostructures) stacked vertically. This composite approach allows each individual layer to be thin enough to maintain good electrostatic control and fit within the reduced device volume, while the combined stacked structure provides sufficient total channel width to maintain electrical mobility and current drive capability. The heterogeneous material composition also enables optimization of band structure and carrier transport properties.
Data Source
AI summary
A semiconductor device includes a first channel layer and a second channel layer spaced from each other in a first direction and each include a two-dimensional (2D) semiconductor material, a first source electrode between the first channel layer and the second channel layer to be simultaneously in contact with the first channel layer and the second channel layer, a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and simultaneously in contact with the first channel layer and the second channel layer, a first gate electrode arranged in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer, and a first gate insulating layer surrounding the first gate electrode in the first internal space.