2D Material String Driver Layout for Dense Vertical Memory
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Solution Overview
Problem
Conventional vertical memory array technologies face challenges in increasing memory density without causing routing congestion and connection obstacles, as the number of tiers of conductive structures increases.
Innovation Solution
The use of a microelectronic device configuration that includes dielectric structures, a non-planar 2D material structure, gate structures, conductive structures, and contact structures, which allows for enhanced memory density while alleviating routing congestion and connection issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers of conductive structures is increased to enhance memory density, then memory density is improved, but routing complexity and congestion increase
Solution Approach 1:
The patent transitions from planar (2D) transistor arrangements to vertical (3D) stacking architectures, where memory cells are arranged in multiple tiers along the vertical dimension. This allows memory density to increase by exploiting the third dimension rather than expanding laterally, thereby avoiding routing congestion that would result from increased lateral complexity.
Solution Approach 2:
The vertical memory array is segmented into multiple independent tiers, each with its own conductive structures and memory cells. This segmentation allows for modular organization where each tier can be independently managed, reducing the overall routing complexity by localizing connections within each tier rather than requiring complex inter-tier routing for all connections.
2Quantity of substance
If additional tiers of conductive structures are formed to increase memory density, then memory density is improved, but connection paths become congested and more complex
Solution Approach 1:
By stacking memory tiers vertically, the patent provides direct vertical access to each tier through dedicated contact structures. This vertical arrangement ensures that connection paths remain short and direct, maintaining ease of operation despite increased memory density, as each tier can be accessed independently without navigating complex lateral routing paths.
Solution Approach 2:
The patent introduces intermediate contact structures and conductive elements that facilitate direct vertical connections to each memory tier. These intermediary structures act as mediators between the external environment and the stacked memory cells, providing simple access paths that bypass routing congestion and maintain operational ease.
3Quantity of substance
If the vertical memory array includes more tiers of conductive structures, then memory density is improved, but conventional component locations become inadequate
Solution Approach 1:
The patent redistributes components along the vertical dimension, placing different functional blocks (such as string drivers, sense amplifiers, and control logic) at different vertical levels corresponding to different memory tiers. This vertical component placement provides flexibility in adapting the architecture to various memory densities, as components can be positioned optimally relative to the tiers they serve without being constrained by fixed lateral locations.
Data Source
AI summary
A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.