2D Transition Metal Dichalcogenide FET Sub-10nm Channel
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Solution Overview
Problem
Current field-effect transistor technologies face challenges in miniaturization and mass production due to limitations in using two-dimensional materials as channel layers, particularly due to difficulties in forming complete or large two-dimensional film layers and high costs associated with lift-off processes.
Innovation Solution
A field-effect transistor structure utilizing a two-dimensional transition metal dichalcogenide channel layer with a source/drain structure disposed on a substrate, where the channel layer covers the space between the source and drain, and a gate layer is positioned to overlap the channel layer, allowing for precise control of channel length and thickness, enabling efficient deposition and integration into existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two-dimensional materials are used as channel layers to achieve miniaturization and high electron mobility, then device performance and conductivity are improved, but the ability to form complete or large two-dimensional film layers deteriorates
Solution Approach 1:
The patent introduces an intermediary material layer between the substrate and the two-dimensional channel layer to facilitate the formation of complete film layers. This intermediary layer acts as a mediator that enables better adhesion and coverage of the two-dimensional material, resolving the contradiction between achieving high electron mobility through two-dimensional materials and forming complete film layers during manufacturing.
2Adaptability or versatility
If lift-off process is used to preset transistor locations and sizes for two-dimensional material placement, then manufacturing flexibility is improved, but production cost and complexity increase
Solution Approach 1:
Instead of using the conventional lift-off process that requires presetting transistor locations and sizes before placing two-dimensional materials, the patent inverts the approach by directly forming two-dimensional material channels in desired locations through controlled deposition or growth methods. This eliminates the need for complex lift-off processes while maintaining the ability to control transistor locations and sizes.
3Ease of manufacture
If conventional silicon substrate is used in planar FETs and FinFETs to maintain manufacturing compatibility, then ease of manufacture is improved, but device miniaturization and performance improvement are limited
Solution Approach 1:
The patent changes the material parameter from conventional silicon substrate to two-dimensional transition metal dichalcogenide materials for the channel layer. This parameter change enables both continued compatibility with existing fabrication processes and the ability to achieve sub-10 nanometer channel lengths, thereby resolving the contradiction between ease of manufacture and device miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of transistors with channel lengths less than 10 nanometers, improved semiconductor properties, and reduced production costs, facilitating mass production while maintaining performance, by leveraging the semiconductor properties of transition metal dichalcogenides and controlling the thickness of the channel layer through layer-by-layer deposition.
Implementation Method 1
two-dimensional materials, especially the most well-known material 'graphene', show high electron mobility and low resistivity
Implementation Method 2
The gate layer is disposed between the source and the drain and covers the 2D channel layer
Data Source
AI summary
A field-effect transistor structure having two-dimensional transition metal dichalcogenides includes a substrate, a source/drain structure, a two-dimensional (2D) channel layer, and a gate layer. The source/drain structure is disposed on the substrate and has a surface higher than a surface of the substrate. The 2D channel layer is disposed on the source and the drain and covers the space between the source and the drain. The gate layer is disposed between the source and the drain and covers the 2D channel layer. The field-effect transistor having two-dimensional transition metal dichalcogenides is a planar field-effect transistor or a fin field-effect transistor.