2D TMD Transistor Contacts via Selective Dielectric Metallization
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Solution Overview
Problem
The implementation of 2D materials in field effect transistors (FETs) is challenging due to material defects such as vacancies during growth and subsequent fabrication processes, which lead to contact resistance and degrade the performance of transistors, especially as device dimensions decrease.
Innovation Solution
A method for fabricating transistor structures with TMD material layers involves forming a partially metallized layer on a 2D material channel structure by exposing portions of a dielectric layer to plasma treatment, thereby mitigating damage to the channel structure and reducing residual contaminants between the channel and source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS transistor fabrication processing is used on 2D materials, then transistor structures can be formed, but material defects such as vacancies and residual contaminants increase, leading to contact resistance and degraded transistor performance
Solution Approach 1:
The fabrication process is divided into distinct stages: forming the 2D material channel structure, depositing dielectric layers, selectively removing dielectric material to expose channel portions, and forming source/drain contacts. This segmentation allows optimized processing for each stage, minimizing cumulative damage to the 2D material while achieving complete transistor structures.
Solution Approach 2:
Dielectric layers serve as intermediary protective layers between the 2D material channel structure and the source/drain contact formation process. These dielectric layers are selectively removed to expose specific portions of the channel structure, enabling contact formation while protecting other regions from damage and contaminant introduction.
2Reliability
If 2D material channel structures are used in transistors, then excellent short channel properties and high mobility are achieved, but the structures become more susceptible to damage from fabrication processes
Solution Approach 1:
Dielectric layers are deposited on the 2D material channel structure before source/drain contact formation. This preliminary action creates a protective barrier that prevents direct exposure of the fragile 2D material to harsh fabrication processes, reducing damage and contaminant introduction while enabling subsequent contact formation.
Solution Approach 2:
The dielectric layers are selectively removed to expose only specific portions of the 2D material channel structure where source/drain contacts need to be formed. This local quality approach ensures that the 2D material is exposed only where necessary for electrical contact, minimizing overall exposure to damaging processes while maintaining excellent short channel properties in protected regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of damage to the channel structure and minimizes residual contaminants, leading to improved transistor performance and scalability, particularly in nanosheet transistors where mobility and subthreshold slope are critical.
Implementation Method 1
performing a plasma treatment of a second portion of the third layer, wherein the plasma treatment forms a conductive body from the second portion
Data Source
AI summary
Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. While a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (S/D) electrode structure that adjoins the first portion. In another embodiment, the dielectric material is an oxide of a Group V-VI transition metal.