2D Channel Transistor Contacts for Lower Resistance Doping
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Solution Overview
Problem
The semiconductor industry faces challenges in advancing semiconductor manufacturing processes to accommodate the increasing complexity and miniaturization of integrated circuits, requiring innovative methods to improve device performance and efficiency while maintaining cost-effectiveness.
Innovation Solution
The method involves a detailed manufacturing process that includes forming a semiconductor device over a substrate with specific layers and structures, such as a bottom dielectric layer, intermediate contact material, spacer films, and sacrificial layers, to create a semiconductor device with a gate structure and channel layer, where the intermediate contact pattern is made of 2D materials like graphene or TMDs, reducing contact resistance and enabling site-specific synthesis of n-type and p-type channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor manufacturing processes are used, then existing device structures can be maintained, but contact resistance remains high and device performance is limited
Solution Approach 1:
The patent changes the material parameter of the contact layer from conventional metals to two-dimensional materials (graphene, TMDs), which fundamentally alters the electrical properties and reduces contact resistance. This material parameter change enables improved device performance while managing manufacturing complexity through selective area growth techniques.
Solution Approach 2:
The patent introduces two-dimensional materials as an intermediary layer between the metal contact and the semiconductor channel. This intermediate layer acts as a mediator that reduces contact resistance and improves charge carrier injection, resolving the contradiction between maintaining simple manufacturing and achieving high device performance.
2Ease of manufacture
If chemical doping is used to create n-type and p-type channels, then device functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces chemical doping methods with electrical doping using the two-dimensional material layer. Instead of introducing chemical dopants that require complex processing, the electrical properties are tuned through electric fields and material selection, simplifying the manufacturing process while improving doping precision and control.
Solution Approach 2:
The patent changes the method of controlling electrical properties from chemical composition changes to electrical field control and material selection. By using two-dimensional materials with different band structures (graphene for n-type, TMDs for p-type), the patent achieves type control without chemical doping, reducing manufacturing complexity while maintaining reliability.
3Productivity
If geometry size is scaled down, then functional density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the contact structure into distinct functional layers: metal contact layer, two-dimensional material layer, and semiconductor channel. This segmentation allows each layer to be optimized independently and grown/processed through specialized techniques, enabling scaling to higher functional densities while managing fabrication complexity through modular processing.
Solution Approach 2:
The patent transitions from planar contacts to vertically stacked contacts with two-dimensional materials, adding a vertical dimension to the contact structure. This dimensional change increases functional density by utilizing the vertical space for low-resistance contact paths while keeping the lateral footprint small, thus improving productivity without proportionally increasing fabrication complexity.
Data Source
AI summary
A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.