2D Semiconductor Transistor Structure for Reduced Hysteresis
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Solution Overview
Problem
Two-dimensional semiconductor FET devices based on silicon oxide gate oxides exhibit significant hysteresis, which affects their performance and efficiency.
Innovation Solution
A two-dimensional semiconductor transistor structure is developed with a gate electrode, a gate insulating layer, an organic dopant layer, a two-dimensional semiconductor layer, and electrodes, where the organic dopant layer is formed by naturally oxidizing triphosphine, diphenylphosphide, or conductive polymers, and is used to reduce hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide gate oxide is used in two-dimensional semiconductor FET devices, then the device structure is simple and manufacturing is easy, but the hysteresis is large which affects performance
Solution Approach 1:
The gate insulating layer is segmented into multiple layers: a first gate insulating layer (silicon oxide) and a second gate insulating layer (high-k dielectric material) disposed on the first gate insulating layer. This segmentation allows each layer to perform its function optimally while reducing overall hysteresis
Solution Approach 2:
The gate insulating structure uses a composite of silicon oxide and high-k dielectric material (such as hafnium oxide, aluminum oxide, or tantalum oxide). This composite structure combines the advantages of both materials: silicon oxide provides good interface characteristics while the high-k dielectric provides superior insulating properties with reduced hysteresis
2Device complexity
If thermal growth silicon oxide is used as gate insulating layer, then the manufacturing process is simple, but the hysteresis is large reducing device efficiency
Solution Approach 1:
The gate insulating layer is divided into a first gate insulating layer formed by thermal growth and a second gate insulating layer formed by atomic layer deposition. This segmentation maintains process simplicity while reducing hysteresis through the combination of layers
Solution Approach 2:
A composite gate insulating structure is formed combining thermally grown silicon oxide with ALD-deposited high-k dielectric material. This composite approach reduces hysteresis while maintaining manufacturing simplicity through sequential deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure reduces hysteresis, improving switching characteristics and reducing power consumption and performance instability, while maintaining high device durability and using silicon dioxide as the gate insulating layer.
Implementation Method 1
The organic dopant layer is obtained by naturally oxidizing at least one of the triphosphine, the diphenylphosphide, the chlorodiphenylphosphine, and the conductive polymer
Data Source
AI summary
A two-dimensional semiconductor transistor includes a gate electrode, a gate insulating layer disposed on the gate electrode, an organic dopant layer disposed on the gate insulating layer and comprising an organic material including electrons, a two-dimensional semiconductor layer disposed on the organic dopant layer, a source electrode disposed on the two-dimensional semiconductor layer, and a drain electrode disposed on the two-dimensional semiconductor layer and spaced apart from the source electrode. A hysteresis of the two-dimensional semiconductor transistor is reduced due to the two-dimensional semiconductor transistor including the organic dopant layer.