2D Material Gate-All-Around Transistor Structure With Self-Aligned Channels
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing processes, particularly in scaling down and high integration density of semiconductor devices like transistors, poses challenges in efficiently forming and patterning complex 2D material layers for advanced transistor structures.
Innovation Solution
The method involves forming a stacked structure with composite channel material layers using self-defined 2D material layers, specifically patterning and growing transition metal dichalcogenides (TMDs) and graphene within defined regions to create complex 2D material layers, which are then integrated into the semiconductor device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If continuously scaling down and high integration density of semiconductor devices are implemented, then device performance and integration capability are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the channel material into multiple thin 2D material layers (e.g., TMD layers and graphene layers) stacked alternately with sacrificial layers. This segmentation enables precise control of each layer's thickness and composition, allowing scaling to smaller dimensions while maintaining manufacturing control through modular layer-by-layer fabrication
Solution Approach 2:
The patent employs a nested structure where complex 2D material layers are formed by alternating stacks of thin 2D material layers and sacrificial layers. The sacrificial layers are embedded within the 2D material stack, creating a nested configuration that simplifies the overall manufacturing process by enabling self-aligned patterning and reducing the number of separate fabrication steps required
2Reliability
If complex 2D material layers are formed for advanced transistor structures, then transistor performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent performs preliminary actions by first forming the complete stacked structure of 2D material layers and sacrificial layers before any patterning or device fabrication steps. The complex 2D material layers are prepared in advance with precise thickness and composition control, and the sacrificial layers are pre-positioned to define future device regions, thereby simplifying subsequent manufacturing steps
Solution Approach 2:
The patent uses sacrificial layers as intermediary elements that facilitate the formation of complex 2D material structures. These sacrificial layers act as mediators during fabrication, enabling self-aligned patterning and serving as temporary structures that guide the formation of the final device geometry. The sacrificial layers are removed after serving their structural and alignment functions, leaving the desired 2D material transistor structures
Data Source
AI summary
A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. The complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. The gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. The source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.