2D Nano Transistor Side Contacts to Prevent Fermi Level Pinning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing feature sizes, leading to issues such as fermi level pinning of metal contacts to the upper half of two-dimensional (2D) material channels, which affects the performance of both p-type and n-type nano-FETs.
Innovation Solution
The formation of nanostructure transistors with metal contacts as side contacts to the 2D material channels, avoiding fermi level pinning by forming metal source/drain regions after replacement gate stacks, thus improving the performance of both p-type and n-type nano-FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal contacts are formed to 2D material channels using conventional top-contact methods, then electrical connection is achieved, but fermi level pinning occurs affecting transistor performance
Solution Approach 1:
The patent transitions from conventional top-contact configuration to side-contact configuration, changing the spatial dimension of metal contact formation. The metal source/drain regions are formed laterally adjacent to the 2D material channel rather than contacting it from above, thereby avoiding fermi level pinning while maintaining electrical connectivity through the side interface
Solution Approach 2:
The patent performs preliminary formation of metal source/drain regions before final gate stack integration. By pre-forming the metal contacts with appropriate work function selection and positioning them laterally adjacent to the channel, the design prevents fermi level pinning from occurring in the first place, rather than attempting to correct it afterward
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent changes the geometric parameters of the transistor structure by adopting side-contact configuration, which allows for optimized lateral spacing between metal regions and 2D material channel. This parameter change enables better process control at reduced feature sizes while maintaining electrical performance and achieving higher integration density
3Stability of the object's composition
If thermal budget is reduced to prevent damage to 2D material, then material integrity is maintained, but metal contact formation becomes more challenging
Solution Approach 1:
The patent performs preliminary formation of metal source/drain regions at lower temperatures before final annealing steps. By pre-positioning the metal contacts laterally adjacent to the 2D material channel and using selective low-temperature deposition techniques, the process maintains 2D material integrity while achieving proper metal contact formation
Solution Approach 2:
The patent changes the temperature parameters during metal contact formation by using lower deposition temperatures and optimized annealing schedules. This allows metal source/drain regions to be formed with appropriate crystallinity and electrical properties while preventing thermal damage to the sensitive 2D material channel
Data Source
AI summary
A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.