2D Semiconductor Transistor Stack for Short-Channel Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance and integration density, particularly in multi-gate transistors with three-dimensional channels, where scaling and short channel effects are difficult to manage.
Innovation Solution
The use of a two-dimensional semiconductor material as a channel in a semiconductor device, combined with a specific transistor structure that includes etch blocking films and wiring structures, allows for improved current control and suppression of short channel effects, enabling high performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional channel transistors are used for scaling, then integration density is improved, but short channel effects become difficult to manage
Solution Approach 1:
The patent transitions from three-dimensional channel transistors to two-dimensional channel transistors, changing the dimensional characteristics of the channel structure. This dimensionality change enables better control over short channel effects while maintaining high integration density through vertical stacking of multiple transistor layers.
2Reliability
If gate length is increased to suppress short channel effects, then short channel effect control is improved, but current control capability deteriorates
Solution Approach 1:
By adopting two-dimensional channel structures, the patent achieves effective short channel effect suppression without increasing gate length. The reduced dimensional confinement in the channel provides better electrostatic control, maintaining current control capability while suppressing short channel effects.
3Reliability
If two-dimensional semiconductor material is used as channel, then mobility is improved and short channel effects are suppressed, but device complexity increases
Solution Approach 1:
The patent combines multiple two-dimensional semiconductor material layers with gate electrodes and source/drain structures into integrated transistor stacks. By merging these components in a vertical configuration, the patent achieves high mobility and short channel effect suppression while managing device complexity through systematic integration.
4Productivity
If vertical stacking of transistors is implemented, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct layers including two-dimensional semiconductor material layers, gate electrodes, and source/drain contacts arranged vertically. This segmentation enables systematic manufacturing of complex three-dimensional transistor stacks through controlled deposition and patterning processes.
Data Source
AI summary
A semiconductor device having high performance and a high degree of integration includes a substrate, a first transistor disposed on the substrate, the first transistor comprising a first active pattern including a first two-dimensional semiconductor material, a first gate electrode through which the first active pattern penetrates, and a first source/drain contact connected to the first active pattern on a side surface of the first gate electrode, a second transistor disposed on an upper surface of the first transistor, the second transistor comprising a second active pattern including a second two-dimensional semiconductor material, a second gate electrode through which the second active pattern penetrates, and a second source/drain contact connected to the second active pattern on a side surface of the second gate electrode, and a first wiring structure interposed between the first transistor and the second transistor, and electrically connecting the first transistor and the second transistor.