Vertical Oxide Semiconductor Memory Channel With 2DEG Confinement
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing integration, operating speed, and yield due to reduced design rules, which are not adequately addressed by conventional transistor designs.
Innovation Solution
The introduction of a semiconductor memory device with vertical channel transistors featuring a channel pattern comprising a first and second oxide semiconductor layer with varying thicknesses and gallium concentrations, along with a gate dielectric pattern, to enhance electrical properties and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional transistor designs are used with reduced design rules, then integration increases, but electrical properties deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to vertical channel structures, changing the dimensional orientation of the transistor channel. This vertical configuration allows the channel to extend in the thickness direction rather than laterally, enabling improved electrical properties while maintaining small footprint for high integration.
Solution Approach 2:
The patent employs a composite oxide semiconductor layer structure consisting of multiple layers with different compositions and thicknesses. Specifically, it uses a first oxide semiconductor layer with a first thickness and a second oxide semiconductor layer with a second thickness greater than the first, creating a heterogeneous structure that optimizes electrical characteristics.
2Ease of manufacture
If oxide semiconductor layers with uniform thickness are used, then fabrication is simplified, but electrical properties such as electron mobility are suboptimal
Solution Approach 1:
The patent applies local quality by creating oxide semiconductor layers with spatially varying thicknesses. The first oxide semiconductor layer has a first thickness while the second oxide semiconductor layer has a second thickness greater than the first, allowing different regions of the channel to have optimized properties for specific electrical characteristics.
Solution Approach 2:
The patent changes the thickness parameter of the oxide semiconductor layers to optimize electrical properties. By setting the second thickness to be greater than the first thickness, the patent adjusts the physical dimensions to achieve improved electron mobility and other electrical characteristics while maintaining fabrication feasibility.
3Device complexity
If single-layer oxide semiconductor structure is used, then device complexity is reduced, but subthreshold swing and threshold voltage are not optimized
Solution Approach 1:
The patent segments the oxide semiconductor channel into multiple distinct layers: a first oxide semiconductor layer and a second oxide semiconductor layer with different thicknesses. This segmentation allows independent optimization of each layer's properties to achieve improved subthreshold swing and threshold voltage characteristics.
Solution Approach 2:
The patent uses a composite structure of multiple oxide semiconductor layers with varying thicknesses to achieve optimized electrical properties. The combination of a thinner first layer and a thicker second layer creates a composite channel structure that improves subthreshold swing and threshold voltage while maintaining reasonable structural complexity.
Data Source
AI summary
Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.