2T-1C Memory Cell Arrays With Reconfigured Bitline Pairs
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Solution Overview
Problem
The scalability of Dynamic Random Access Memory (DRAM) is limited by the difficulty in incorporating capacitors with sufficiently high capacitance into highly-integrated architectures, particularly in 1T-1C configurations, which hinders the adoption of more advanced 2T-1C memory cell configurations that offer improved signal-to-noise and lower power operation.
Innovation Solution
The development of memory arrays utilizing 2T-1C memory cells, which leverage existing structures in DRAM, allowing for quick adoption without substantial modification of established fabrication processes, by configuring wordlines and bitlines in specific orthogonal or intersecting arrangements to facilitate efficient addressing and signal comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1T-1C memory cell configuration is used, then structural simplicity is achieved, but capacitor integration difficulty arises in highly-integrated architectures
Solution Approach 1:
The patent merges the capacitor structure with the transistor structure by forming the capacitor electrodes and dielectric layers within the same fabrication sequence as the transistor, integrating them into a unified memory cell structure that simplifies manufacturing while maintaining the 1T-1C configuration
Solution Approach 2:
The capacitor structure is designed to serve multiple functions: storing charge for memory operation, being formed using the same fabrication processes as the transistor, and integrating seamlessly with the bitline and wordline structures, thereby achieving versatility in both function and manufacturing
2Reliability
If 2T-1C memory cell configuration is used, then signal-to-noise ratio and power efficiency are improved, but fabrication process complexity increases
Solution Approach 1:
The patent segments the memory cell into distinct functional regions: first and second transistors with separate gates, capacitors with specific electrode configurations, and associated bitlines and wordlines, allowing each component to be optimized independently while maintaining overall integration
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of capacitor electrodes and dielectric layers to achieve the 2T-1C configuration without proportionally increasing the planar footprint, thereby managing fabrication complexity through spatial optimization
Data Source
AI summary
Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.