2T-2C Memory Cell Layout for Higher DRAM Scalability
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Solution Overview
Problem
The scalability of Dynamic Random Access Memory (DRAM) is limited by the difficulty in incorporating capacitors with sufficiently high capacitance into highly-integrated architectures, and existing 1T-1C memory cell configurations lack efficient mechanisms to eliminate crosstalk and enhance sense signal magnitude.
Innovation Solution
The development of 2T-2C memory cell configurations with vertically or laterally stacked components, eliminating the need for a reference bitline and doubling the sense signal magnitude, while reducing mechanisms of 'disturb' such as crosstalk between adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1T-1C memory cell configuration is used, then structural simplicity is achieved, but scalability to highly-integrated architectures is limited due to difficulty in incorporating capacitors with sufficiently high capacitance
Solution Approach 1:
The patent transitions from planar 1T-1C configuration to a three-dimensional stacked 2T-2C configuration, utilizing vertical stacking to increase integration density while maintaining capacitor capacitance requirements. This dimensional change allows the memory cell to achieve higher integration without compromising the electrical performance of capacitors.
Solution Approach 2:
The patent combines two capacitor cells into a single memory cell structure with shared transistors and common bitlines. By merging adjacent capacitor cells and sharing control transistors and bitline infrastructure, the design achieves higher integration density while maintaining the necessary capacitance values through the stacked architecture.
2Productivity
If 2T-2C memory cell configuration is used, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent implements shared control transistors and common bitline infrastructure that serve multiple capacitor cells. The control transistor gates are connected to common wordlines, and bitlines are shared between adjacent memory cells, allowing a single transistor structure to control multiple capacitors and reducing overall device complexity despite increased integration density.
Solution Approach 2:
The patent segments the memory array into multiple memory cells, each containing stacked transistors and capacitors. This segmentation allows independent operation and control of individual memory cells while sharing common infrastructure, thereby managing device complexity through modular organization.
3Ease of operation
If conventional memory cell configuration is used, then reference bitline is required for comparison, but this increases area and reduces efficiency
Solution Approach 1:
The patent extracts and eliminates the separate reference bitline from the memory cell structure by implementing differential sensing within the 2T-2C cell itself. The two capacitor cells within each memory cell serve as differential pairs, allowing direct comparison of their electrical properties without requiring an external reference bitline, thereby reducing area while maintaining comparison efficiency.
Data Source
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AI summary
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.