2T-2S SRAM Cell Using Selector Devices for Density
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Solution Overview
Problem
Conventional SRAM devices require a significant area for storage due to the use of four transistors, limiting storage density and consuming more power due to higher capacitance and leakage, especially in the front-end process.
Innovation Solution
The implementation of a 2T-2S SRAM cell that replaces NMOS transistors with selector devices or threshold switches, reducing the number of transistors to two and integrating selector devices in the back-end process, which consumes less area and exhibits lower capacitance, resulting in improved dynamic switching and static power performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM uses four transistors per cell, then reliable data storage is achieved, but area consumption increases significantly
Solution Approach 1:
The patent merges the functionality of four separate transistors into a combined 2T-2S structure where two transistors work together with two selector devices. The cross-coupled transistor pair shares common source and drain connections, reducing the total transistor count while maintaining the bistable latch functionality through the interaction between transistors and selector devices.
Solution Approach 2:
Selector devices are introduced as intermediary components that enable the reduced transistor configuration to function as SRAM. These selector devices, positioned in the back-end process, provide the necessary switching and storage functionality that would otherwise require additional transistors, allowing area reduction while preserving data retention capability.
2Reliability
If four transistors are used in SRAM cell, then data retention is maintained, but power consumption increases due to higher capacitance and leakage
Solution Approach 1:
By merging four transistors into a 2T-2S configuration, the total capacitance of the memory cell is reduced since fewer transistor gates need to be charged and discharged. The combined structure maintains data retention through the cross-coupled arrangement where the two transistors and two selector devices create stable states with lower overall power requirements.
Solution Approach 2:
The patent changes the operational parameters by replacing standard NMOS transistors with selector devices that have optimized electrical characteristics. These selector devices exhibit lower leakage current and reduced capacitance, fundamentally altering the power consumption profile while maintaining the voltage-dependent resistance states necessary for data storage.
3Ease of manufacture
If NMOS transistors are used in front-end process, then conventional SRAM functionality is achieved, but area and power efficiency are reduced
Solution Approach 1:
The patent segments the SRAM fabrication process into front-end and back-end portions. The front-end contains two transistors fabricated using conventional processes, while the back-end contains two selector devices added subsequently. This segmentation allows the benefits of reduced area and power consumption without completely abandoning established manufacturing techniques.
Solution Approach 2:
The invention adds a temporal and structural dimension to the fabrication process by integrating back-end selector devices after the front-end transistor layer is complete. This multi-stage approach allows the selector devices to be positioned in the back-end process, enabling area reduction while maintaining compatibility with conventional front-end manufacturing.
Data Source
AI summary
A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.