2-Transistor Memory Cell Structure for Compact Neural Network Arrays
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Solution Overview
Problem
Conventional memory devices face challenges in implementing neural networks due to issues with area efficiency and performance.
Innovation Solution
A memory device with a compact structure using 2-T memory cells and a memory array configuration that improves area efficiency and memory performance for neural network implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory devices are used to implement neural networks, then basic memory storage function is achieved, but area efficiency and performance are insufficient
Solution Approach 1:
The patent combines multiple memory cells into a shared column structure where multiple 2T memory cells share a common bit line and read circuitry. This merging approach reduces the total area required for neural network implementation while maintaining the necessary memory capacity and computational performance.
Solution Approach 2:
The memory device is designed with multi-functional capabilities where the same memory array and read circuitry can perform both traditional memory storage operations and neural network computations (multiply-accumulate operations). This universality eliminates the need for separate dedicated hardware for different functions, improving area efficiency.
2Ease of manufacture
If conventional memory structures are used, then basic functionality is maintained, but area efficiency deteriorates
Solution Approach 1:
The memory array is segmented into multiple 2T memory cells organized in a grid structure with separate word lines and bit lines. This segmentation allows for systematic manufacturing using standard CMOS processes while enabling compact packing of memory cells to reduce overall device area.
Solution Approach 2:
The patent transitions from planar 1T memory cell structures to vertically stacked 2T memory cell structures, utilizing the third dimension (vertical stacking) to increase storage density without proportionally increasing the footprint area, thereby improving area efficiency.
3Productivity
If conventional memory devices are used, then basic storage is achieved, but memory performance for neural networks is insufficient
Solution Approach 1:
The patent extracts the read circuitry and bit line from each individual memory cell and shares them across multiple memory cells in a column. This extraction reduces the complexity of individual memory cell structures while enabling parallel read operations that improve overall memory performance for neural network computations.
Solution Approach 2:
The 2T memory cell structure incorporates the storage function within the transistor gates themselves, where the gate of one transistor serves as the storage node for the other transistor. This self-service approach eliminates the need for separate dedicated storage capacitors, simplifying the structure while maintaining functionality.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory cell and a second memory cell, each of the first and second memory cells including a first transistor including a first region and a first charge storage structure separated from the first region; a second transistor including a second region formed over the first charge storage structure; a first data line coupled to the first memory cell configured to provide a first sum based on current on the first data line during a memory operation; a second data line coupled to the second memory cell configured to provide a second sum based on current on the second data line during the memory operation; and an output circuit to provide output information based on values of the first and second sums.