Two-Transistor NVM Cell Scaling via Differential Read
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Solution Overview
Problem
As semiconductor processes scale down, non-volatile memory (NVM) performance is hindered by design complexity, cycle time, cost, retention, and operating margins, particularly in achieving high performance at reduced critical dimensions.
Innovation Solution
A novel two-transistor (2T) NVM cell using channel hot electron injection and band-to-band hot hole injection for programming and erasing, with a differential read scheme, allowing for a gate oxide thickness of 50 Angstroms or less, and incorporating N-channel and P-channel transistors sharing a floating gate, enabling efficient operation at reduced dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional NVM structures are used, then memory storage is achieved, but design complexity increases and scaling becomes difficult
Solution Approach 1:
The patent combines N-channel and P-channel transistors into a single 2T NVM cell structure that shares common components (gate oxide, floating gate, substrate), reducing overall device complexity while maintaining non-volatile memory functionality. This merged structure achieves better scalability compared to conventional separate transistor designs.
Solution Approach 2:
The 2T NVM cell structure serves multiple functions: it provides non-volatile memory storage, supports both programming and erasing operations, and enables differential reading schemes. This multi-functional design reduces the need for separate dedicated structures for each operation, simplifying overall device architecture.
2Area of moving object
If critical dimension is scaled down, then area is reduced, but NVM performance deteriorates
Solution Approach 1:
The patent changes the gate oxide thickness parameter to 50 Angstroms or less, enabling the NVM cell to function properly at reduced critical dimensions. This parameter change allows the device to maintain performance while achieving smaller area, directly addressing the scaling challenge.
Solution Approach 2:
The patent introduces a vertical dimension solution by using thin gate oxide (50A or less) to enable scaling in the lateral dimension. This dimensional approach allows the memory cell to achieve smaller footprint area while maintaining electrical performance through optimized vertical field effects in the thin oxide layer.
3Productivity
If gate oxide thickness is reduced, then scalability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a gate oxide thickness of 50 Angstroms or less as an optimized parameter that balances scalability with manufacturability. This specific thickness value represents a parameter optimization that enables scaling while remaining achievable with standard semiconductor manufacturing processes of the time.
4Ease of operation
If conventional read schemes are used, then simple operation is maintained, but read margin decreases
Solution Approach 1:
The patent segments the read operation into a differential scheme where N-channel and P-channel transistor currents are read separately and compared. This segmentation allows each transistor to contribute to the read signal, effectively doubling the useful signal and improving read margin while maintaining operational simplicity through standardized differential circuit techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances scalability, maintains high performance, and increases read margin, making the memory cell logic-compatible and multi-time programmable, suitable for applications requiring low area and thin gate oxide.
Implementation Method 1
The 2T NVM cell can be programmed by channel hot electron injection (CHEI) and/or channel hot hole induced hot electron (CHHIHE)
Implementation Method 2
erased through band-to-band hot hole (BBHH) injection and/or Fowler-Nordheim (FN) electron ejection
Implementation Method 3
The N-channel and P-channel transistor may share a common floating gate structure (FG)
Data Source
AI summary
A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.