2T0C DRAM Structure for 3D Memory Density Scaling
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Solution Overview
Problem
The existing dynamic random access memory (DRAM) structure with one transistor and one capacitor (1T1C) faces limitations in size reduction and three-dimensional stacking of the capacitor structure, hindering the achievement of higher storage density.
Innovation Solution
A method for fabricating a semiconductor structure that includes forming a thin-film stack, creating grooves for write transistors and bit lines, and eliminating the need for a capacitor by forming a 2-transistor-0-capacitor (2T0C) structure, which maximizes storage density by using a capacitor-free design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a traditional 1T1C DRAM structure is used, then the device can store data, but the size reduction and three-dimensional stacking are limited by the capacitor structure
Solution Approach 1:
The patent removes the capacitor component from the traditional 1T1C DRAM structure, extracting the storage function and replacing it with a transistor-based storage mechanism. This elimination of the capacitor enables significant size reduction and allows for three-dimensional stacking configurations that were previously constrained by capacitor geometry.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure by eliminating the capacitor's spatial constraints. The write transistor and storage node are arranged in vertical stacking configurations, enabling utilization of the third dimension for increased storage density without the horizontal space requirements of traditional capacitor structures.
2Volume of moving object
If the capacitor structure is reduced in size, then storage density improves, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent changes the fundamental structural parameters by replacing the capacitor with a transistor-based storage mechanism. This parameter change allows for different dimensional scaling relationships where the storage element size is determined by transistor gate dimensions rather than capacitor plate dimensions, enabling more predictable scaling behavior and manufacturing precision control.
Solution Approach 2:
The patent uses standard transistor fabrication processes to create the storage node, effectively copying proven transistor manufacturing techniques rather than requiring new capacitor fabrication processes. This approach leverages existing manufacturing precision capabilities while achieving the desired size reduction for higher storage density.
Data Source
AI summary
Embodiments provide method for fabricating a semiconductor structure, and a semiconductor structure. The method includes: providing a substrate, a thin-film stack structure being formed on the substrate; forming a first groove and a second groove in the thin-film stack structure, and forming write transistors in the first groove, the second groove extending along a first direction, and the second groove being positioned between adjacent two of the write transistors in a second direction; removing a part of the thin-film stack structure by etching using the second groove to form a first hole and a second hole respectively, forming a write word line in the first hole, and forming a write bit line in the second hole; forming a first via on an upper surface of the thin-film stack structure, and forming a storage node in the first via; and forming a read transistor, a read bit line and a lead.