2T0C Memory Cell with Single Bit Line for Dense Integration
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Solution Overview
Problem
Existing 2T0C-based memory cells require two bit lines and two word lines, making it difficult to reduce the feature size and integrate memory cells effectively.
Innovation Solution
A 2T0C-based memory cell design using a single bit line and two transistors, where data storage and retrieval are controlled by word lines and the bit line voltage, allowing for a parasitic capacitance-based storage mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional 2T0C-based memory cell is configured with two bit lines and two word lines, then data storage and retrieval functions are achieved, but the feature size cannot be reduced and integration density remains low
Solution Approach 1:
The patent extracts and eliminates one bit line from the conventional two-bit-line configuration, reducing the number of interconnect lines while maintaining memory functionality through alternative control mechanisms using the remaining bit line in combination with two word lines
Solution Approach 2:
The single bit line is designed to serve multiple functions by combining it with different word lines for both data storage and retrieval operations, allowing the same physical line to participate in different operational modes depending on the active word line configuration
2Productivity
If the number of bit lines and word lines is reduced to decrease feature size, then integration density improves, but device functionality may be compromised
Solution Approach 1:
The patent transitions from a two-dimensional configuration with separate bit lines to a three-dimensional control scheme where two word lines and one bit line interact in a stacked manner, effectively using vertical stacking to compensate for the reduced number of horizontal interconnect lines
Solution Approach 2:
The word lines are used to pre-configure the transistor states and prepare the memory cell for subsequent data operations through the single bit line, enabling functionality to be achieved through preparatory control actions rather than through multiple simultaneous bit lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a smaller feature size of 12F^2 per bit, enabling the memory cell to be stacked in multiple layers, thereby improving integration density without increasing physical space.
Implementation Method 1
a 2T0C-based memory cell may store data by using a parasitic capacitance formed by the two transistors
Data Source
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AI summary
The present disclosure relates to a 2T0C-based memory cell. The 2T0C-based memory cell includes a first transistor and a second transistor connected through a storage node, a first word line connected to the first transistor and controlling an on/off state of the first transistor through an operation of applying a voltage, a second word line connected to the second transistor and controlling an on/off state of the second transistor such that data stored in the memory cell are read, and a single bit line connected to the first transistor and the second transistor and allowing the storage node to be charged or discharged depending on a voltage applied to the single bit line.