2T0C Memory Cell With Single Bit Line for Dense Integration

The patent merges the functions of two bit lines into a single bit line by utilizing the complementary operation of two transistors. The first transistor handles write operations while the second transistor handles read operations, both sharing the same single bit line. This consolidation reduces the number of interconnect lines required, thereby reducing the feature size from the conventional configuration that requires two bit lines and two word lines to the optimized configuration with one bit line and two word lines.

The single bit line serves multiple functions by being shared between two transistors that operate at different times. During write operations, the first transistor uses the bit line to charge the storage node, and during read operations, the second transistor uses the same bit line to sense the stored data. This multi-functional usage of the bit line eliminates the need for separate dedicated lines, enabling feature size reduction while maintaining full data storage and retrieval functionality.

The patent combines the bit line functions into a single shared line that is used by both transistors. The first transistor connects to the storage node through the single bit line for write operations, and the second transistor connects to the same bit line for read operations. This merging of bit line resources reduces the total number of interconnect lines per memory cell, thereby increasing the number of memory cells that can be integrated in a given area.

The patent transitions from a planar two-bit-line configuration to a vertically stacked transistor arrangement where both transistors share the same bit line in the horizontal plane but are positioned at different vertical levels. This three-dimensional stacking approach allows the memory cell to maintain its data storage functionality while reducing the footprint area, thereby improving integration density.

The patent extracts and eliminates one bit line from the conventional two-bit-line configuration. By removing the redundant bit line and redistributing its functionality to the remaining single bit line through coordinated transistor operation, the design achieves smaller feature size while maintaining data storage and retrieval capabilities.

The patent introduces dynamic operation where the single bit line's function changes over time - serving as a write line when the first transistor is active and as a read line when the second transistor is active. This temporal division of labor allows the static physical infrastructure (single bit line) to support dynamic operational requirements that would traditionally require duplicate static infrastructure, enabling feature size reduction.