2T0C Semiconductor Memory Structure Without DRAM Capacitors
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Solution Overview
Problem
Conventional DRAM structures require complex capacitor fabrication processes, which hinder efficiency and integration density due to the need for one transistor per capacitor, whereas a 2T0C embedded DRAM structure with two transistors can simplify these processes by utilizing the transistor gate as a natural capacitor.
Innovation Solution
A method for fabricating a 2T0C semiconductor structure involves forming two transistor arrays on a semiconductor substrate with corresponding bit and word lines, eliminating the need for capacitors by leveraging the transistor gate's charge storage capability, thereby simplifying fabrication procedures and increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 1T1C structure is used, then storage function is achieved, but fabrication complexity and time increase due to extensive capacitor fabrication
Solution Approach 1:
The patent extracts and eliminates the capacitor component from the conventional 1T1C DRAM structure, transitioning to a 2T0C structure where two transistors replace the transistor-capacitor combination. This removal of the capacitor simplifies the fabrication process by eliminating extensive capacitor fabrication steps while maintaining the storage function through the gate capacitance of the transistors themselves.
Solution Approach 2:
The transistor gate in the 2T0C structure serves multiple functions: it acts as both the control element for transistor operation and as the storage element (natural capacitor) for charge storage. This multi-functionality eliminates the need for separate capacitor structures, reducing fabrication complexity while achieving the same storage objective.
2Area of stationary object
If conventional 1T1C structure is used, then storage capability is provided, but integration density decreases due to capacitor space requirements
Solution Approach 1:
By extracting and removing the dedicated capacitor structure from the cell, the patent eliminates the space that would be occupied by capacitor plates and dielectric layers. The storage function is maintained using the inherent gate capacitance of the transistors, which occupies minimal space compared to conventional capacitors, thereby significantly improving integration density.
Solution Approach 2:
The patent merges the storage function into the transistor structure itself, where the gate of each transistor serves as the storage element. This consolidation eliminates the need for separate capacitor structures and their associated space requirements, allowing for higher integration density in the DRAM array.
3Productivity
If capacitor fabrication processes are included, then storage function is achieved, but fabrication time increases
Solution Approach 1:
The patent extracts and eliminates the capacitor fabrication processes from the manufacturing sequence. By transitioning to a 2T0C structure, the time-consuming steps of capacitor dielectric deposition, electrode formation, and capacitor patterning are removed from the fabrication flow, directly improving productivity and reducing total fabrication time.
Solution Approach 2:
The patent discards the conventional capacitor fabrication processes entirely, recovering the time and resources that would have been spent on those steps. The storage function is achieved through the transistor gates, which are formed as part of the standard transistor fabrication process, thereby eliminating dedicated capacitor fabrication time while maintaining storage capability.
Data Source
AI summary
Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; forming first word lines, each of the plurality of first semiconductor pillars being connected to a corresponding one of the first word lines and a corresponding one of the plurality of first bit lines; forming a second transistor array on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, and the plurality of first semiconductor pillars being corresponding to the plurality of second semiconductor pillars one to one; and forming second word lines and second bit lines to form a 2T0C semiconductor structure.