2T1R Memory Cell Layout for Uniform Gate Potential
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Solution Overview
Problem
The layout design of word lines in semiconductor memory leads to non-negligible power consumption and instability in writing or reading operations due to differences in electric potential between gates and manufacture process defects, causing signal transmission abnormalities.
Innovation Solution
A data storage cell design with a conductive line directly connecting the gates of transistors to equalize electric potential, reducing resistance in word lines and preventing signal abnormalities by overlapping and staggering conductive lines with gate electrode lines, and using a two-transistor one-resistor bit cell structure to enhance driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the length of word lines is increased to cover more data storage cells, then the coverage area is improved, but power consumption increases and voltage stability deteriorates
Solution Approach 1:
The patent divides the gate electrode lines into multiple segments, each controlled by separate word lines. This segmentation allows shorter individual word lines to cover the same total area, reducing the power consumption and voltage drop associated with long continuous word lines while maintaining comprehensive coverage of data storage cells.
2Adaptability or versatility
If multiple layers are disposed between gate and word line to enable complex routing, then routing flexibility is improved, but electric potential uniformity deteriorates
Solution Approach 1:
The patent implements equipotential connections by directly connecting gate electrode lines to word lines through contact plugs, ensuring that all gate electrodes receive the same electric potential. This eliminates potential differences caused by multiple intermediate layers, maintaining signal integrity and uniformity across the memory array.
3Adaptability or versatility
If gate electrode lines are made longer to connect more cells, then connectivity is improved, but signal transmission reliability deteriorates due to manufacturing defects
Solution Approach 1:
The patent segments the gate electrode lines into shorter sections, each independently connected to word lines. This reduces the length of individual conductive paths, minimizing the impact of manufacturing defects and signal degradation while maintaining connectivity to all data storage cells through the segmented architecture.
Data Source
AI summary
The invention discloses a data storage cell. The data storage cell includes a storage structure, a first transistor, and a second transistor. A first end of the storage structure is electrically connected to a bit line. The first transistor includes a first gate, a first drain, and a first source. The second transistor includes a second gate, a second drain, and a second source. The first gate is electrically connected to the second gate. A second end of the storage structure is electrically connected to the first drain and the second drain. The first source and the second source are electrically connected to a source line.