2T1R RRAM Cell Design for Low Voltage Crossbar Arrays
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Solution Overview
Problem
Conventional 1T1R RRAM cells face limitations in RESET current and body effect, requiring larger transistors and higher voltages for low voltage operations, which increases area size and power consumption.
Innovation Solution
The implementation of 2T1R RRAM cells with at least one NMOS and one PMOS transistor, connected in series with the RRAM device, enhances RESET current and reduces body effect without increasing area size, using an inverter to control both transistors and reduce routing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 1T1R RRAM cells are used, then device density is improved, but RESET current is insufficient and body effect increases
Solution Approach 1:
The single transistor in 1T1R is segmented into two transistors (NMOS and PMOS) operating in parallel, where each transistor handles different voltage polarities. This segmentation allows the circuit to overcome the body effect limitation of single-transistor designs while maintaining high device density through efficient use of the crossbar array structure.
Solution Approach 2:
The patent employs asymmetric transistor pairing with different transistor types (NMOS and PMOS) that have complementary characteristics. The NMOS transistor handles positive voltage operations while the PMOS transistor handles negative voltage operations, creating an asymmetric but balanced system that optimizes RESET current for both polarities without increasing area.
2Reliability
If larger transistors are used to increase RESET current, then RESET current is improved, but area size increases
Solution Approach 1:
The patent merges the functionality of two transistors (NMOS and PMOS) into a single parallel pair that operates together to achieve high RESET current. By combining the strengths of both transistor types and utilizing their parallel operation, the design achieves the RESET current of larger transistors while maintaining the area footprint of compact transistor structures.
Solution Approach 2:
The patent changes the electrical parameters of the transistor pair by selecting complementary transistor types with different threshold voltages and current characteristics. This parameter optimization allows each transistor to operate in its optimal range, achieving high combined RESET current without requiring oversized individual transistors.
3Reliability
If higher voltages are used to overcome body effect, then body effect is reduced, but power consumption increases
Solution Approach 1:
The PMOS transistor acts as an intermediary that compensates for the body effect experienced by the NMOS transistor. By providing an alternative conduction path with complementary characteristics, the PMOS transistor mediates the voltage requirements and reduces the need for high voltage operations, thereby lowering power consumption while maintaining effective body effect compensation.
4Reliability
If 2T1R RRAM cells are used, then RESET current and body effect are improved, but device complexity increases
Solution Approach 1:
The NMOS-PMOS parallel pair serves multiple functions simultaneously: it provides high RESET current, compensates for body effect, handles both positive and negative voltage polarities, and maintains compatibility with standard crossbar array fabrication. This multi-functionality reduces the need for additional specialized components, thereby limiting the increase in overall device complexity.
Data Source
AI summary
Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.