2T1R RRAM Cell Structure for Wide Operating Voltage Spans
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Solution Overview
Problem
The traditional 1T1R RRAM cell structure faces challenges with a wide voltage span for different operations, leading to compromised device reliability and increased cell area, which hinders high-density integration and industrial application.
Innovation Solution
A 2T1R cell structure is introduced, comprising two parallel-connected transistors with different electrical characteristics, each optimized for specific voltage requirements, and a resistive switching device, fabricated using standard CMOS processes to maintain cell area equivalence with traditional 1T1R cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional 1T1R cell structure is used, then the cell area is small, but the voltage span for different operations is wide which compromises device reliability
Solution Approach 1:
The single transistor in the traditional 1T1R structure is segmented into two parallel transistors (T1 and T2) with different threshold voltages. T1 is optimized for high-voltage operations (forming/reset) while T2 is optimized for low-voltage operations (set/read), allowing each transistor to operate within its optimal voltage range and thereby improving overall device reliability without increasing cell area
2Reliability
If the voltage span for different operations is reduced, then device reliability improves, but cell area increases which hinders high-density integration
Solution Approach 1:
Different regions of the transistor system are assigned different electrical characteristics: T1 has a higher threshold voltage (e.g., 2.5V) suitable for high-voltage forming/reset operations, while T2 has a lower threshold voltage (e.g., 1.5V) suitable for low-voltage set/read operations. This local differentiation of electrical properties allows the system to handle multiple voltage requirements without expanding the overall cell area
3Device complexity
If a single transistor is used to control all operations, then the cell structure is simple, but the transistor must sacrifice performance for reliability due to wide voltage span requirements
Solution Approach 1:
The control function is segmented from a single transistor into two specialized transistors working in parallel. This segmentation allows T1 to handle high-voltage forming/reset operations with optimized performance, while T2 handles low-voltage set/read operations, eliminating the need for a single transistor to compromise performance across a wide voltage span
4Reliability
If two transistors are added to the cell structure, then various voltage requirements can be met, but the cell area increases significantly
Solution Approach 1:
The two transistors T1 and T2 are merged into a parallel configuration sharing common source and drain regions, along with shared select lines (S1B and S2B). This merging approach allows both transistors to be integrated within the footprint of a traditional single-transistor cell, meeting various voltage requirements without significant area increase
Data Source
AI summary
The present invention disclosures a RRAM cell structure, comprising a first transistor and a second transistor which are connected in parallel and commonly connected to a resistive switching device; wherein, the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source; the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source; the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device. The present invention uses cell area of a traditional 1T1R to manufacture a 2T1R cell structure, which can take into account various operating voltage requirements of the resistive switching device simultaneously, so as to significantly improve cell performances thereof.