2T2M MRAM Layout to Prevent Back Hopping in Writes
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Solution Overview
Problem
Existing MRAM technologies face challenges in miniaturization and layout optimization, particularly in preventing back hopping issues that affect write capability due to varying switching pulse requirements among MTJs, which are exacerbated by Joule heating during write operations.
Innovation Solution
A 2T2M MRAM circuit design where two MTJs share a common drain terminal, connected in parallel with transistors, enhancing memory capacity and preventing series connection to mitigate back hopping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MTJs are series-connected to increase memory capacity, then memory capacity per unit area is improved, but back hopping issue occurs due to varying switching pulse requirements causing write capability degradation
Solution Approach 1:
The patent segments the MTJ array into multiple independent parallel groups, where each group contains MTJs connected in parallel rather than series. This segmentation allows each group to operate independently with uniform switching characteristics, preventing back hopping while maintaining high memory capacity through increased number of parallel groups.
Solution Approach 2:
The patent transitions from a single-dimension series connection to a multi-dimensional parallel arrangement. By organizing MTJs in parallel across multiple word lines and bit lines, the design achieves high capacity without the cumulative switching pulse issues inherent in series connections, effectively solving back hopping through dimensional reorganization.
2Ease of operation
If switching pulse is increased to switch MTJs with higher switching requirements, then switching capability is improved, but Joule heating increases causing inability to switch MTJs with lower requirements
Solution Approach 1:
The patent applies local quality by ensuring that MTJs within each parallel group have matched switching characteristics through localized design and fabrication control. This allows each group to be switched with a uniform pulse that is optimized for its specific switching requirements, avoiding both the back hopping caused by excessive pulses and the insufficient switching caused by low pulses.
3Area of stationary object
If conventional series-connected MTJ design is used, then layout utilization is reduced, but write operation reliability is maintained
Solution Approach 1:
The patent merges multiple MTJs in parallel within shared word lines and bit lines, combining their switching operations under unified control. This merging approach increases layout utilization by reducing the number of separate control lines needed while maintaining write reliability through the uniform switching characteristics of parallel-connected MTJs with matched properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves memory capacity per unit layout area and resolves back hopping issues, thereby enhancing write capability and maintaining reliable data storage in MRAM circuits.
Implementation Method 1
an external magnetic field is applied in the operation of MRAM to control magnetization direction of MTJs and implement different tunnel magnetoresistances (TMR), so as to define different storage states for storing digital data
Implementation Method 2
excess switching pulse may cause Joule heating issue, unable to rotate the second MTJ to the predetermined magnetization direction, so that data can't be written correctly into MRAM units
Data Source
AI summary
A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and the second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a first bit line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a second bit line, and a source line connected to the first source and the second source.