2T2M MRAM Layout for Higher Density and Lower Write Voltage

The patent utilizes the vertical dimension by stacking MTJs at both source and drain terminals of transistors in the BEOL layers. This three-dimensional arrangement allows memory cells to be stacked vertically rather than only laid out horizontally, significantly increasing memory capacity per unit layout area while maintaining standard planar transistor footprints.

The patent nests multiple MTJ memory cells within the vertical space above a single transistor footprint. By placing MTJs at both source and drain terminals and utilizing multiple BEOL layers, the design effectively nests multiple storage elements within the spatial envelope of a conventional single-MTJ cell, doubling or tripling the memory capacity without increasing the lateral area.

The patent segments the write operation into two independent paths: one through the source-terminal MTJ and another through the drain-terminal MTJ. This segmentation allows selective activation of only the necessary write path based on the required storage state transition, reducing the total write voltage and current required compared to conventional single-path write operations, thereby lowering power consumption while maintaining reliability.

The patent implements dynamic write voltage control by enabling selective activation of source or drain terminal write paths depending on the desired state transition. This dynamic approach allows the circuit to use minimal voltage for simple transitions while providing full write capability only when necessary, optimizing the balance between write reliability and power consumption.