2T2MTJ MRAM Cell Voltage Sensing Write Margin
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Solution Overview
Problem
Current magnetic random access memory (MRAM) technologies face challenges in achieving high-speed operations due to limited write and read margins, requiring accurate current control for write operations and suffering from low read signals, which complicates both write and read processes.
Innovation Solution
The MRAM design incorporates a 2-Transistor-2-MTJ (2T2MTJ) cell configuration with mirror-symmetrically arranged write wirings and parallel-symmetrically arranged magnetic resistance elements, allowing for improved write and read margins by using two magnetic resistance elements per memory cell to enhance operational speed through voltage-based sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current sensing method is used to read MTJ resistance, then the read operation can be performed, but the read signal is not great and a long time is required for current-voltage conversion
Solution Approach 1:
The patent replaces the conventional current sensing method with a voltage sensing method. Instead of measuring current through the MTJ element and performing current-voltage conversion, the invention applies a voltage to the MTJ element and directly measures the resulting voltage signal. This substitution eliminates the time-consuming current-voltage conversion process and provides a stronger read signal, directly addressing the technical contradiction between measurement precision and time loss.
2Productivity
If the MR ratio is low (30% to 50%), then the memory cell structure is simple, but the read signal is not great and high speed read operation cannot be performed
Solution Approach 1:
The patent employs voltage sensing instead of current sensing to directly measure the resistance state of the MTJ element. By applying a read voltage and measuring the resulting voltage signal, the system achieves both high read operation speed and strong read signal strength, resolving the contradiction between productivity and measurement precision without requiring a higher MR ratio.
3Reliability
If accurate current control is required for write operations, then the write margin is limited, but the memory cell structure remains simple
Solution Approach 1:
The patent introduces a write wiring that carries a write current generated outside the memory cell. This intermediary wiring allows the write current to be generated by a dedicated write circuit rather than requiring complex current control within each memory cell. The write wiring acts as a mediator that delivers the required current to the MTJ element, thereby improving the write margin without increasing the complexity of the memory cell structure itself.
4Ease of operation
If the sensing amplifier becomes large in size, then the current sensing method can be implemented, but the overall device area increases
Solution Approach 1:
The patent replaces the current sensing method with a voltage sensing method. By measuring voltage directly across the MTJ element rather than measuring current and performing conversion, the system eliminates the need for large sensing amplifiers. The voltage sensing approach provides sufficient sensing capability with much smaller circuitry, thereby reducing the overall device area while maintaining ease of operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operations by widening the write margin and improving the read signal, allowing for faster and more accurate data storage and retrieval without increasing the memory cell area or altering the surrounding circuitry.
Implementation Method 1
An MTJ element used in a memory cell of an MRAM includes a pinned magnetic layer whose magnetization is pinned in an optional direction, and a free magnetic layer whose magnetization is variable by an external magnetic field. The pinned magnetic layer and the free magnetic layer are laminated such that a tunnel insulating film is put between them. In the MRAM, a 1-bit storage data is assigned to the relative magnetization state between the pinned magnetic layer and the free magnetic layer.
Implementation Method 2
a write wiring for applying a write current, and a magnetic resistance element having one end connected to the write wiring
Data Source
AI summary
A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.