2T2R Binary Weight Cell with High On/Off Ratio
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Solution Overview
Problem
Current hardware accelerators for machine learning applications face inefficiencies in matrix vector multiplications due to the use of static random access memory (SRAM) and non-volatile memory options like RRAM, STT-MRAM, which suffer from low on/off ratios and high variation, making them power inefficient and incompatible for efficient weight representation.
Innovation Solution
A weight cell configuration is introduced, comprising two STT memory devices and n-type field effect transistors (FETs) with cross-coupling, allowing for a high on/off ratio and complementary output, enabling efficient matrix vector multiplication through the use of magneto tunnel junctions (MTJs) in a resistive memory element, optimizing current flow based on logical values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If non-volatile memory options such as RRAM, FLASH or STT-MRAM are used for weight representation, then memory efficiency is improved, but on/off ratio becomes low and variation increases
Solution Approach 1:
The patent combines a resistive memory element with a transistor to form an integrated weight cell structure. The transistor's gate is connected to the resistive element, creating a coupled system where the transistor controls current flow through the resistive element, thereby achieving high on/off ratio while maintaining non-volatile memory properties.
Solution Approach 2:
The weight cell uses a composite structure combining resistive memory material (for non-volatile storage) with transistor material (for high on/off ratio control). This composite approach leverages the strengths of both materials: the resistive element provides non-volatility while the transistor provides high current modulation capability.
2Reliability
If SRAM is used for weight representation, then on/off ratio is maintained, but area and power consumption increase
Solution Approach 1:
The patent uses a single transistor instead of the six transistors required by SRAM, effectively using a simpler, less resource-intensive component structure. This reduces the area requirement significantly while maintaining the essential on/off ratio functionality through the transistor-resistive element coupling.
Solution Approach 2:
The patent extracts only the essential components needed for weight representation: one transistor and one resistive memory element. By removing the redundant components present in SRAM (additional transistors and capacitors), the design achieves compact area while preserving the core functionality of high on/off ratio.
3Use of energy by moving object
If non-volatile memory options are used for weight representation, then memory efficiency is improved, but programming voltage compatibility becomes problematic
Solution Approach 1:
The transistor acts as an intermediary between the control circuitry and the resistive memory element. It mediates the programming process by controlling current flow through the resistive element, enabling voltage-compatible programming operations while maintaining non-volatile memory efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the on/off ratio of the weight cell, allowing for efficient analog multiplication operations with reduced power consumption and improved compatibility, enabling effective inference operations in machine learning applications.
Implementation Method 1
enabling efficient matrix vector multiplication through the use of magneto tunnel junctions (MTJs) in a resistive memory element
Implementation Method 2
two STT memory devices and n-type field effect transistors (FETs) with cross-coupling
Data Source
AI summary
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.