2T2R RRAM Bit Line Layout to Prevent Transistor Breakdown
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Solution Overview
Problem
Existing 2T2R resistive random access memory (RRAM) structures face issues with transistor breakdown due to high leakage voltage when a single RRAM is operated, as both RRAMs share a bit line, leading to potential breakdown of the other transistor.
Innovation Solution
The semiconductor structure connects first and second memristors in each memory cell to different bit lines, with adjacent rows of memristors sharing the same bit line, allowing independent voltage control and reducing leakage, while maintaining the same array density without increasing cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two RRAMs in a 2T2R structure are connected to the same bit line, then the array density is maintained, but the transistor faces the risk of breakdown caused by high leakage voltage when a single RRAM is operated
Solution Approach 1:
The bit lines are segmented into first bit lines and second bit lines. First memristors connect to first bit lines while second memristors connect to second bit lines, separating the voltage paths and preventing leakage voltage from affecting transistors in adjacent memory cells. This segmentation resolves the contradiction by maintaining array density while eliminating the breakdown risk.
2Ease of operation
If first memristors in one row and second memristors in adjacent row are connected to the same bit line, then the array density is maintained, but voltage control independence is lost
Solution Approach 1:
The bit line segmentation allows independent voltage control of first and second memristors through separate first and second bit lines, while still maintaining array density by connecting memristors from adjacent rows to the same bit line type. This resolves the contradiction between operational independence and reliability.
3Reliability
If separate bit lines are used for all memristors, then transistor breakdown is prevented, but the cell area increases
Solution Approach 1:
The segmentation into first and second bit lines provides separate voltage paths for different memristor types, preventing transistor breakdown while maintaining compact cell area. The segmented architecture allows efficient space utilization by assigning specific bit lines to specific memristor rows.
Data Source
AI summary
A semiconductor structure and a preparation method thereof are provided. The semiconductor structure includes: a substrate; a plurality of memory cells arranged in a first direction and a second direction, each of the memory cells including a first transistor, a first memristor, a second transistor, and a second memristor; where the first and second directions are parallel to a plane of the substrate and intersect; and a plurality of first and second bit lines extending in the first direction. In every two adjacent rows of memory cells arranged in the first direction, all the first memristors in a first row and all the second memristors in a second row are connected to a same first bit line, and all the second memristors in the first row and all the first memristors in the second row are connected to a same second bit line.