2-TFT Active Matrix Capacitive Fingerprint Sensor
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Solution Overview
Problem
Existing fingerprint sensors face challenges in achieving high sensitivity and accuracy while minimizing the impact on optical performance and requiring fewer active elements to reduce complexity and space, while also addressing parasitic capacitances and process variations.
Innovation Solution
The implementation of active matrix capacitive fingerprint sensors with 1-TFT or 2-TFT pixel architectures, which integrate charge over multiple cycles and utilize minimal TFTs per pixel to enhance sensitivity and accuracy, and include drive/readout circuits with feedback capacitance and operational amplifiers to cancel parasitic capacitances, thereby reducing the impact on display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more TFTs are used per pixel to improve sensing accuracy and sensitivity, then measurement precision improves, but device complexity increases
Solution Approach 1:
The pixel circuit is segmented into two distinct TFT components: a first TFT for charge transfer controlled by row select lines, and a second TFT for signal readout controlled by column output lines. This segmentation allows each TFT to perform a specialized function, achieving accurate fingerprint sensing with only two TFTs per pixel rather than requiring a larger number of TFTs for multiple functions.
Solution Approach 2:
The first TFT serves multiple purposes: it acts as a switch for charge transfer from the sensing electrode to the floating diffusion node, and also functions as part of the charge amplification mechanism. This multi-functionality reduces the overall TFT count while maintaining sensing accuracy.
2Measurement precision
If more active elements are used to improve sensing performance, then measurement precision improves, but area occupied increases
Solution Approach 1:
The circuit merges the charge transfer function and the readout function into a single integrated pixel structure with only two TFTs. The first TFT handles charge transfer while the second TFT handles signal readout, combining multiple functions into a compact arrangement that minimizes pixel area while maintaining high sensing performance.
Solution Approach 2:
The patent utilizes the floating diffusion node as an intermediate charge storage element, effectively adding a temporal dimension to the charge transfer process. Charges are transferred during a specific time window controlled by the first TFT, then read out later by the second TFT, allowing compact spatial arrangement while maintaining performance.
3Measurement precision
If parasitic capacitances are not compensated then device complexity remains low, but measurement precision deteriorates
Solution Approach 1:
The circuit employs feedback through the floating diffusion node, where the capacitance changes at the sensing electrode are transferred and amplified through the TFT cascade. The feedback mechanism naturally compensates for parasitic capacitances by measuring differential changes, reducing the need for additional complex compensation circuits.
Solution Approach 2:
The floating diffusion node acts as an intermediary element between the sensing electrode and the readout circuitry. It serves as a charge storage node that isolates the sensing process from the readout process, allowing parasitic capacitances to be minimized and compensated without requiring complex additional circuits.
Data Source
AI summary
Embodiments described herein include an input device including an array of sensing pixels configured to sense an input object in a sensing region. Each of the sensing pixels includes a sense element and a first transistor, wherein the first transistor includes a gate terminal connected to a row select line and a second terminal connected to the sense element. Each of the sensing pixels also includes a second transistor, wherein the second transistor includes a gate terminal connected to the sense element and the second terminal of the first transistor, and wherein the second transistor further includes a second terminal connected to a column output line.