2TnR RRAM Cell With Horizontal Stacked Resistive Switching Layers
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Solution Overview
Problem
Traditional RRAM cells with a 1T1R structure are limited to binary storage and face challenges in achieving high-density integration for multi-value storage due to the vertical stacking structure of resistive switching layers, which increases cell area when trying to connect multiple cells in parallel.
Innovation Solution
A 2TnR RRAM cell structure is proposed, featuring two vertical channel transistors and resistive switching cells with a horizontal stack structure, where electrodes are shared between adjacent cells, allowing for binary and multi-value storage functions while maintaining a compact cell area, compatible with standard CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple resistive switching cells are connected in parallel horizontally to achieve multi-value storage, then the storage capacity is improved, but the cell area is significantly increased
Solution Approach 1:
The patent transitions from horizontal parallel connection to vertical stacking connection. Multiple resistive switching cells are connected in parallel through vertical stacking in the thickness direction, allowing multi-value storage while maintaining a compact cell footprint. The electrode layers are arranged vertically with alternating patterns, enabling n-cell parallel connection without increasing planar area significantly.
2Productivity
If a vertical stacking structure is used for resistive switching layers, then the integration density is improved, but the cell area increases when connecting multiple cells in parallel
Solution Approach 1:
The patent merges multiple resistive switching cells into a single integrated stack structure. The electrode layers and resistive switching layers are combined in a vertical sandwich structure where multiple cells share common electrodes and are connected through the stacking direction. This merging approach achieves high integration density while controlling cell area by utilizing the third dimension (thickness) for cell multiplication.
3Adaptability or versatility
If a 1TnR structure is implemented with horizontal parallel connection, then multi-value storage is achieved, but the manufacturing complexity increases due to process rules
Solution Approach 1:
The patent segments the resistive switching cell stack into repeating units that can be systematically fabricated. Each unit consists of electrode-resistive switching layer-electrode sequences that can be deposited in a modular fashion using standard CMOS back-end processes. The vertical stacking allows systematic segmentation into n parallel cells while maintaining compatibility with existing manufacturing process rules.
Data Source
AI summary
The present invention is to provide a RRAM cell, comprising: two transistors which are coupled and resistive switching cells, and the number of the resistive switching cells is n; wherein electrodes of the resistive switching cells are connected in sequence to form a horizontal stack structure, and the same electrode is shared between any two adjacent resistive switching cells, the gates of the two transistors are used for applying different control signals respectively, the sources of the two transistors are connected together and used for applying a source signal jointly, drains of the two transistors are connected to one end of each of electrodes of different resistive switching cells which the number thereof is m in the resistive switching cells which the number thereof is n respectively, and the other ends of the electrodes of the resistive switching cells which the number thereof is n are used for applying different bit signals respectively. According to the present invention. Based on vertical channel transistors and resistance switching cells with a horizontal stacked structure, a 2TnR RRAM is formed in the present invention, which can simultaneously realize binary and multi value storage functions according to different operation timings, and cell area is controllable. It can be used to realize a high-density RRAM array and chip.