3.5D Semiconductor Package for Memory-Logic Bandwidth Bottlenecks
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Solution Overview
Problem
The von Neumann structure experiences bottlenecks in data transfer between memory and logic due to increased logic calculations, particularly in fields requiring high-speed data transfer like artificial intelligence calculations and high-performance computing.
Innovation Solution
A semiconductor package design with a package substrate, interposers, and through vias that facilitate high bandwidth communication between logic and memory chips, including a first memory chip horizontally spaced from the logic chip and a second memory chip vertically spaced from the logic chip, with interposers connecting multiple semiconductor chips in a 3.5D configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory and logic functions are separated in von Neumann structure, then functional specialization is improved, but data transfer time increases causing bottleneck phenomenon
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3.5D packaging architecture, utilizing vertical stacking dimensions to place memory chips and logic chips in three-dimensional space. This spatial reconfiguration reduces horizontal wiring length while maintaining functional separation, thereby decreasing data transfer time without sacrificing functional specialization.
Solution Approach 2:
The patent introduces interposers as intermediary components between memory chips and logic chips. These interposers provide standardized connection interfaces and signal routing pathways, enabling efficient data transfer between separated memory and logic functions while managing the complexity of inter-chip communications.
2Productivity
If the number of I/O terminals between memory and logic is increased, then communication bandwidth is improved, but package complexity increases
Solution Approach 1:
The patent segments the high I/O bandwidth requirement into multiple independent chip-to-chip connections. Instead of requiring one complex high-speed interface, the system uses multiple parallel connections between memory chips and logic chips, distributing the bandwidth requirement across several simpler interfaces managed by interposers.
Solution Approach 2:
Interposers serve as intermediary components that manage and organize multiple I/O connections between memory and logic chips. They provide standardized interfaces and routing capabilities that simplify the complexity of establishing numerous high-speed connections, making the package more manageable while maintaining high communication bandwidth.
3Speed
If wiring length between memory and logic is reduced, then data transfer speed is improved, but package area constraints are worsened
Solution Approach 1:
The patent utilizes the vertical dimension in 3.5D packaging to reduce horizontal wiring length. By stacking memory chips and logic chips vertically with interposers, the data transfer path transitions from long horizontal routes to shorter vertical connections, improving data transfer speed while efficiently utilizing package area.
Data Source
AI summary
A semiconductor package may include a package substrate, a first interposer on the package substrate, a first semiconductor chip and a second semiconductor chip that are on the first interposer, a second interposer on the first semiconductor chip, a third semiconductor chip on the second interposer, and a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.