3-Level Flash Memory Cell Layout for Wider Threshold Margins
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices, particularly 4-level memory cells, are prone to errors due to small margins between threshold voltage distributions, leading to reduced reliability compared to 2-level cells, which may outweigh the benefits of increased storage capacity.
Innovation Solution
A nonvolatile semiconductor memory device with 3-level memory cells, utilizing a memory array, page buffer, and row decoder to control threshold voltages based on first, second, and third bits, with even and odd strings of memory cells connected to common bit lines for programming and read operations, allowing for distinct threshold voltage distributions and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 4-level memory cells are used to increase storage capacity, then the amount of data stored per area increases, but the margins between threshold voltage distributions become small leading to errors and reduced reliability
Solution Approach 1:
The memory cells are divided into even strings and odd strings, with each string containing memory cells that can be independently controlled. This segmentation allows for separate programming and reading operations on different strings, enabling more reliable 4-level memory operation by isolating interference between cells
Solution Approach 2:
The patent introduces a dual-bit line system (even and odd bit lines) that operates in parallel dimensions. By connecting memory cells in even strings to even bit lines and memory cells in odd strings to odd bit lines, the system achieves higher storage capacity while maintaining distinguishable threshold voltage distributions through spatial separation
2Quantity of substance
If 4-level memory cells are used to increase storage capacity, then more data can be stored, but the small margins between threshold voltage distributions cause reading errors
Solution Approach 1:
Different strings of memory cells are assigned different local characteristics through separate bit line connections. Even strings are connected to even bit lines and odd strings to odd bit lines, allowing each group to have optimized local reading conditions that improve threshold voltage distinction accuracy
Solution Approach 2:
The patent uses sense amplifiers as intermediary components between the memory cells and the external system. These sense amplifiers detect and amplify the small voltage differences corresponding to different threshold voltage distributions, improving the precision of reading 4-level memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3-level memory cells provide higher integration and reliability compared to both 2-level and 4-level cells, with larger margins between threshold voltage distributions, enhancing data storage capacity and operational stability.
Implementation Method 1
Various alternative techniques exist for trapping electrons in floating gate FG, including Fowler-Nordheim tunneling, channel-initiated secondary electron injection, and channel hot electron injection, for example.
Implementation Method 2
Various alternative techniques exist for trapping electrons in floating gate FG, including Fowler-Nordheim tunneling, channel-initiated secondary electron injection, and channel hot electron injection, for example.
Implementation Method 3
the electrons trapped in floating gate FG tend to elevate the threshold voltage of memory cell MC because these electrons partially cancel out an electrical field generated by the voltage applied to control gate CG
Data Source
AI summary
A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines. The first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations. The device programs and reads data in a pair of memory cells using three bits of data corresponding to three threshold voltage distributions of the 3-level nonvolatile memory cells.