3-Level UPS Topology Reducing Switching Losses

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Solution Overview

Problem

Conventional UPS systems face inefficiencies due to high switching losses, limited surge handling, and increased complexity and cost with advanced semiconductors, as well as challenges in controlling hybrid topologies that affect power factor correction and inverter regulation.

Innovation Solution

A 3-level UPS topology that introduces Zero Voltage Switching (ZVS) at Power Factor Correction (PFC) switch turn-on and inverter switch turn-off, reducing switching losses and enhancing overall efficiency by synchronizing the switching operations across multiple phases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional switching operations are used in UPS systems, then the system can operate with standard semiconductor devices, but switching losses increase and efficiency decreases

Engineering Contradiction:
Improveswitching lossesVSAvoidsystem efficiency
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent applies preliminary action by ensuring the DC bus voltage is driven to zero before the PFC switch turns on and before the inverter switch turns off. This pre-conditioning of the voltage state eliminates voltage-current overlap during switching transitions, thereby eliminating switching losses without requiring advanced semiconductor devices.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the voltage parameter of the DC bus by actively controlling it to be zero during critical switching moments. This parameter modification (voltage = 0) during specific time windows enables lossless switching operations for both the PFC and inverter stages, directly resolving the contradiction between switching losses and system efficiency.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If advanced semiconductor devices are used to reduce switching losses, then switching efficiency improves, but device complexity and cost increase

Engineering Contradiction:
Improveswitching lossesVSAvoidsemiconductor complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent employs standard, readily available semiconductor devices rather than expensive advanced semiconductors. By using conventional devices with proper switching control (driving DC bus voltage to zero), the system achieves low switching losses without the complexity and high cost of advanced semiconductor technologies, effectively replacing expensive components with cheaper alternatives through clever control strategies.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Adaptability or versatility

If hybrid topologies are used for power factor correction and inverter regulation, then system functionality improves, but control complexity increases

Engineering Contradiction:
Improvepower factor correction capabilityVSAvoidcontrol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the control of the PFC stage and inverter stage by using a unified control strategy that drives the DC bus voltage to zero for both operations. This combined approach simplifies the control architecture compared to separate independent controls, reducing overall control complexity while maintaining full power factor correction and inverter regulation functionality through coordinated operation.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The 3-level UPS topology achieves higher efficiency by minimizing switching losses and providing effective power factor correction and surge handling, while reducing the complexity and cost associated with advanced semiconductors.

Implementation Method 1

A 3-level UPS topology that introduces Zero Voltage Switching (ZVS) at Power Factor Correction (PFC) switch turn-on and inverter switch turn-off, reducing switching losses and enhancing overall efficiency

Methodology Applied
Scientific EffectZero Voltage Switching (ZVS):

Data Source

PatentEP3161925B13-level power topology
Publication Date: 2021.08.04 SCHNEIDER ELECTRIC IT CORP
  • EP3161925B1 patent drawingFigure 1
  • EP3161925B1 patent drawingFigure 2
  • EP3161925B1 patent drawingFigure 3

AI summary

According to one aspect, embodiments of the invention provide a power supply system comprising an input configured to receive input AC power from an input power source, an output configured to provide output AC power to a load, a converter coupled to the input and configured to convert the input AC power into converted DC power, a first DC bus coupled to the converter and configured to receive the converted DC power, an inverter coupled to the first DC bus and the output and configured to convert DC power from the first DC bus into the output AC power, a first DC switch circuit coupled between the first DC bus and neutral and a controller coupled to the first DC switch circuit and configured to operate the first DC switch circuit such that voltage on the first DC bus is zero during switching operation of the converter and the inverter.