3-Phase Clock Recovery Using Pulse-Suppressed Multiphase Sampling
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Solution Overview
Problem
The existing clock generation circuits in multi-wire, multi-phase data communication links, such as those used in C-PHY interfaces, face limitations in speed and reliability due to variations in signal transition times and timing skews, which affect the ability to accurately recover clock information and maintain high data transfer rates as signaling frequencies increase.
Innovation Solution
A method and apparatus that configure a clock recovery circuit to generate a first clock signal with pulses for each symbol at a specific frequency, adjust the loop delay to suppress pulse generation for certain symbols, and provide a second clock signal with pulses for all symbols, allowing for improved clock recovery and data capture in a 3-wire, 3-phase interface, thereby addressing the limitations of existing clock generation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay circuits are employed to ensure stable signaling states before sampling, then reliability of clock recovery is improved, but transmission rate is limited by the delay values
Solution Approach 1:
The patent divides the clock recovery function into multiple parallel CDR circuits operating at different phases. Each CDR circuit processes a subset of symbols with reduced delay requirements, and their outputs are combined to achieve the complete clock recovery function. This segmentation allows each individual circuit to operate with shorter delays while maintaining overall system reliability.
Solution Approach 2:
The patent employs periodic sampling at multiple phase offsets across different CDR circuits. By distributing sampling instances periodically across different time phases, the system achieves comprehensive symbol capture without requiring excessive delay in any single circuit, thereby maintaining high transmission rates while ensuring reliable clock recovery.
2Reliability
If maximum delay values are used to accommodate signal transitions, then all conductors assume stable signaling state before sampling, but the transmission rate is limited
Solution Approach 1:
The patent segments the delay accommodation function across multiple CDR circuits, each handling a portion of the total delay requirement. This distribution allows the system to achieve the necessary stable state assurance without any single circuit introducing excessive delay that would limit the overall transmission rate.
Solution Approach 2:
The patent transitions from a single-dimensional time delay approach to a multi-dimensional solution by introducing phase diversity. Multiple CDR circuits operate simultaneously at different phase offsets, effectively adding a phase dimension to the delay management problem. This allows the system to achieve stable sampling without being constrained by maximum delay values in the time domain alone.
3Productivity
If signaling frequencies are increased to improve data transfer rate, then communication speed is improved, but clock recovery ability is limited by timing skews
Solution Approach 1:
The patent segments the clock recovery function across multiple CDR circuits that each handle high-frequency signaling with reduced timing skew impact. By distributing the recovery function, the system can accommodate higher signaling frequencies without any single circuit being overwhelmed by timing skews, thus maintaining clock recovery ability at higher data transfer rates.
Solution Approach 2:
The patent implements dynamic phase adjustment capabilities in the multiple CDR circuits, allowing the system to adapt to varying timing skews that occur at different signaling frequencies. This dynamic adaptation enables reliable clock recovery across a wide range of high-frequency operating conditions, supporting increased data transfer rates without sacrificing recovery ability.
Data Source
AI summary
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.