32-bit Arithmetic Support Using 16-bit Multiply and Addition
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Solution Overview
Problem
Modern low-power central processing units (CPUs) optimized for low energy consumption primarily support 16-bit arithmetic, limiting their ability to perform full 32-bit arithmetic operations without significant overhead, which is necessary for certain signal-conditioning applications like FFT and FIR filtering.
Innovation Solution
The implementation of specific instructions such as 'shift-right add signed/unsigned' and 'shift-right add signed/signed' operations in a low-energy accelerator processor, allowing for 32-bit operations using 16-bit multiplication capabilities without the need for a full barrel shifter, thereby reducing power consumption and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 32-bit arithmetic operations are implemented in low-power CPUs, then computational capability is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent segments 32-bit arithmetic operations into multiple 16-bit operations. Specifically, it divides a 32-bit multiply-accumulate operation into four separate 16-bit multiply operations and combines their results through addition and shifting. This segmentation allows the use of simpler, lower-power 16-bit arithmetic units while achieving 32-bit computational capability.
Solution Approach 2:
The patent performs partial actions by breaking down the full 32-bit operation into smaller 16-bit steps. It executes multiple partial 16-bit multiply operations (four separate multiplications) and combines them to achieve the complete 32-bit result, using only the necessary computational effort for the target application rather than implementing full 32-bit hardware.
2Adaptability or versatility
If 32-bit arithmetic operations are implemented in low-power CPUs, then computational capability is improved, but silicon area and gate count increase
Solution Approach 1:
The patent segments 32-bit arithmetic operations into multiple 16-bit operations. Specifically, it divides a 32-bit multiply-accumulate operation into four separate 16-bit multiply operations and combines their results through addition and shifting. This segmentation allows the use of simpler, lower-power 16-bit arithmetic units while achieving 32-bit computational capability.
Solution Approach 2:
The patent makes the 16-bit arithmetic unit universal by using it to perform both 16-bit and 32-bit operations. The same 16-bit multiply and add units are used for all arithmetic operations, with 32-bit functionality achieved through coordinated sequences of 16-bit operations rather than dedicated 32-bit hardware.
3Adaptability or versatility
If full 32-bit arithmetic is supported, then application versatility is improved, but overhead to basic 16-bit operators increases
Solution Approach 1:
The patent segments 32-bit arithmetic operations into multiple 16-bit operations. Specifically, it divides a 32-bit multiply-accumulate operation into four separate 16-bit multiply operations and combines their results through addition and shifting. This segmentation allows the use of simpler, lower-power 16-bit arithmetic units while achieving 32-bit computational capability.
Data Source
AI summary
Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.