Block-Kronecker QC-LDPC Layout for 3888-Bit 802.11 Code Blocks
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Solution Overview
Problem
Current communication systems using LDPC codes are limited by the longest block length supported in 802.11 standards, which restricts the gain that can be achieved in radio channels.
Innovation Solution
The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 and a code rate of 5/6, which doubles the block length of the longest code supported in 802.11 standards, enhancing encoding and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond 1944 bits to achieve higher coding gain, then error correction performance is improved, but compatibility with existing 802.11 standards is lost and system complexity increases
Solution Approach 1:
The patent divides the 3888-bit block into two separate 1944-bit blocks, each processed by existing 802.11 compliant LDPC encoders/decoders. This segmentation allows the system to achieve longer effective block length and improved error correction performance while maintaining compatibility with existing standards and avoiding the need for completely new complex encoding/decoding hardware.
Solution Approach 2:
The patent embeds two 1944-bit LDPC code blocks within a single 3888-bit transmission frame, creating a nested structure where the existing standard-compliant code blocks are contained within a larger transmission unit. This nesting approach allows the system to leverage existing 802.11 infrastructure while achieving enhanced performance through the effective doubling of block length.
2Reliability
If a new LDPC code with block length 3888 is implemented to double the maximum block length, then coding gain is enhanced, but encoding and decoding process complexity increases
Solution Approach 1:
The encoding process segments the 3888-bit block into two independent 1944-bit blocks, each encoded using existing 802.11 LDPC encoders. The decoding process similarly segments received blocks into pairs of 1944-bit blocks for independent decoding. This segmentation reduces encoding/decoding complexity by reusing existing standardized algorithms rather than implementing new complex 3888-bit LDPC processors.
Solution Approach 2:
The patent makes existing 802.11 LDPC encoders and decoders universal by enabling them to process both individual 1944-bit blocks and paired 3888-bit blocks. This multi-functionality allows the same hardware/software to achieve both standard compliance and enhanced performance without requiring separate complex processing paths.
3Reliability
If the block length is extended to 3888 bits, then gain in radio channels is improved, but the longest block length limit in 802.11 standards becomes a restricting factor
Solution Approach 1:
The patent nests two 1944-bit standard-compliant code blocks within a single 3888-bit transmission frame, allowing the system to exceed the 1944-bit block length limit while maintaining 802.11 compatibility. The nested structure enables the outer 3888-bit frame to carry the payload of two inner 1944-bit blocks, effectively doubling the achievable block length without violating standard constraints.
Solution Approach 2:
The patent transitions from extending block length in one dimension (single continuous block) to using multiple dimensions (parallel processing of two separate blocks). By treating the 3888-bit block as two concurrent 1944-bit blocks processed through the same standard-compliant pipeline, the system achieves longer effective length without requiring a single monolithic block that would violate standards.
Data Source
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AI summary
An apparatus may include a transmitter (120) and one or more processors (2010). The one or more processors (2010) may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors (2010) may encode data using the second parity check matrix. The transmitter (120) may be configured to transmit the encoded data.