3-bit and 4-bit Per-Cell Memory Programming Algorithm
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Solution Overview
Problem
As memory cells decrease in size and memory arrays increase in density, maintaining data integrity becomes challenging in semiconductor memory systems, particularly in multi-state flash memory devices that store multiple bits per cell, due to the complexity of programming and verifying threshold voltage distributions.
Innovation Solution
A single memory die is designed to include memory cells that can be programmed as 3-bit-per-cell or 4-bit-per-cell using logic circuits that implement specific programming algorithms, allowing for flexible configuration between 3-bit and 4-bit data storage by modifying the gray code and verify levels, enabling efficient storage of multiple data states without requiring separate logic circuits for each configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase density, then storage capacity increases, but data integrity deteriorates
Solution Approach 1:
The patent changes the programming parameters by implementing different verify level configurations (3-bit verify levels for 3-bit-per-cell mode, 4-bit verify levels for 4-bit-per-cell mode) and adjusting threshold voltage distributions to maintain data integrity across different storage densities and cell sizes
2Manufacturing precision
If separate logic circuits are designed for 3-bit and 4-bit programming, then programming precision improves, but device complexity increases
Solution Approach 1:
The patent implements a universal logic circuit that can operate in both 3-bit-per-cell and 4-bit-per-cell modes by dynamically selecting and applying appropriate verify level configurations and programming algorithms, eliminating the need for separate dedicated circuits for each mode
Solution Approach 2:
The patent introduces dynamic configuration capabilities where the programming algorithm adaptively adjusts verify levels and programming parameters based on the selected operating mode (3-bit or 4-bit per cell), allowing a single circuit to optimize performance for different storage requirements
Data Source
AI summary
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.