3D 1T1C Stacked DRAM Layout for Higher Density Memory Cells
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Solution Overview
Problem
Current DRAM architectures face challenges in scaling due to the need for large capacitors, which limits memory density, and existing configurations such as trench-like or capacitor over bitline (COB) capacitors complicate further miniaturization.
Innovation Solution
The development of 3D stacked DRAM structures where each memory cell comprises a transistor and capacitor in a single plane, allowing for vertical stacking and reduced fabrication complexity, with capacitors configured in various shapes to enhance surface area and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-layer DRAM architecture is used, then fabrication process is simpler, but memory density is limited
Solution Approach 1:
The patent transitions from traditional planar single-layer DRAM architecture to a three-dimensional stacked architecture where memory cells are arranged in multiple vertical layers. Each layer contains complete 1T1C memory cells with transistors and capacitors formed in alternating conductive and insulating layers, enabling vertical stacking to increase memory density without proportionally increasing fabrication complexity through standardized repetitive layer formation processes
2Productivity
If large capacitors are used to maintain storage capacity, then capacitor size increases, but memory density decreases
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to accommodate multiple capacitors above the substrate plane. Capacitors are formed in upper conductive layers separated by insulating layers, allowing memory cells to be stacked vertically rather than arranged horizontally. This dimensional transition enables increased memory density while maintaining individual capacitor sizes necessary for storage capacity
Solution Approach 2:
The patent implements a nested structure where multiple conductive layers containing capacitors are stacked within a vertical column above a single substrate area. Each capacitor is nested within its own insulating layer, creating a compact vertical arrangement where capacitors are positioned one above another, effectively nesting storage elements to maximize memory density without increasing planar footprint
3Ease of manufacture
If trench-like capacitors or COB capacitors are formed, then capacitor functionality is achieved, but fabrication complexity increases
Solution Approach 1:
The patent employs a universal layer formation process where alternating conductive and insulating layers are deposited and patterned repeatedly to create multiple memory cell layers. The same fabrication steps—forming conductive layers, forming insulating layers, and patterning—are applied universally across all layers, enabling consistent production of 3D stacked memory cells with integrated capacitors without requiring specialized trench formation or COB capacitor processes
Solution Approach 2:
The patent merges the formation of transistors and capacitors into a unified layer structure where conductive layers serve dual purposes: forming transistor electrodes in lower regions and forming capacitor electrodes in upper regions. Insulating layers simultaneously provide electrical isolation for transistors and serve as capacitor dielectric materials, combining multiple functional requirements into integrated layer formations that simplify fabrication while enabling 3D stacking
Data Source
AI summary
Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.