3D 1TIR Memory Structure With GAA Transistors for Higher Density
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Solution Overview
Problem
Existing 3D NVRAM memories face challenges in achieving high density, efficient electrostatic control, and consistent current levels due to bulky access transistors, resistive lines, and design irregularities, limiting their performance and scalability.
Innovation Solution
A 3D NVRAM memory structure utilizing Gate-All-Around (GAA) transistors with independently controllable gates and insulated conductive lines, avoiding resistive lines within memory levels, and employing semiconductor nanowires with all-around gates to enhance density and current output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional access transistors are used in 3D NVRAM memory, then the memory structure can be implemented, but the access transistors are bulky and limit the achievable maximum density of memory elements
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures, utilizing the vertical dimension to enhance transistor control and reduce footprint. The FinFET geometry allows the channel to be controlled from three sides, enabling higher density while maintaining electrostatic control.
Solution Approach 2:
The patent implements a nested structure where multiple memory levels are stacked vertically, with each level containing memory elements and access transistors. The source lines are formed within the stack structure itself, nesting the interconnects within the active memory region to maximize space utilization.
2Quantity of substance
If gates are made in direct contact on active areas to increase density, then density improves, but the distance between gates and active areas must be large enough to enable etching
Solution Approach 1:
The patent performs preliminary formation of the source lines within the stack structure before forming the gates. This preliminary action establishes the spatial relationships and etching pathways needed to subsequently create gates in direct contact with active areas at minimal distances.
Solution Approach 2:
The patent utilizes vertical stacking to achieve gate-to-active-area proximity in the lateral dimension while maintaining manufacturing feasibility through vertical etching pathways. The three-dimensional architecture allows gates to contact active areas from above without requiring large lateral separation.
3Ease of manufacture
If source lines are made within the stack before etching gates, then integration is improved, but the distances between lines must be large enough to dispose two transistor gates between them
Solution Approach 1:
The patent applies different material compositions to different regions of the source lines. The portions of source lines located between gates in different memory levels have different compositions than other portions, enabling selective etching and closer spacing while maintaining electrical connectivity and structural integrity.
4Reliability
If source lines are made of doped silicon, then conductivity is improved, but the lines become very resistive and reduce current output
Solution Approach 1:
The patent employs composite material structures for source lines, combining highly conductive materials such as metal layers with doped silicon regions. This composite approach achieves low overall resistance while maintaining compatibility with the semiconductor device fabrication process and electrostatic control requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The GAA transistor design achieves high memory element density, efficient electrostatic control, and improved current levels, enabling independent addressing and reducing resistive constraints, thus enhancing memory performance and scalability.
Implementation Method 1
improved electrostatic control
Implementation Method 2
first electrically-conductive portions, each crossing at least two memory levels and being electrically coupled to first ends of the semiconductor nanowires
Data Source
AI summary
A memory is structured in lines and columns over several superimposed levels. Each level includes an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels. The memory also includes conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of the column; first conductive lines, each connected to the conductive portions of the same column; and word lines each extending in the same level while coupling together the gates of the same line and located in said level.