3D 2T Memory Cell Layout for Higher Density With Single Access Line
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints, especially when attempting to shrink memory cell size.
Innovation Solution
The development of a memory device with a 4F2 cell footprint that includes two-transistor (2T) memory cells with a charge storage structure, allowing for a smaller size and improved processing efficiency through a single access line and cross-point gain cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then device storage density is improved, but physical limitations and fabrication constraints worsen
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical stack configuration. Multiple memory cells are stacked vertically along the Z-axis, with bit lines extending in the X-direction and word lines in the Y-direction, creating a three-dimensional cross-point architecture. This dimensional change allows significantly higher storage density within the same footprint while avoiding the fabrication challenges of extreme miniaturization in 2D.
Solution Approach 2:
The patent implements a nested structure where multiple decks of memory cells are stacked vertically, with each deck containing multiple memory cells. The bit lines, word lines, and charge storage structures are nested in specific spatial relationships - bit lines pass through openings in dielectric layers, word lines are positioned at different vertical levels, and charge storage structures are embedded within the stack. This nesting enables high density while maintaining manufacturability.
2Quantity of substance
If conventional memory cell structures are used, then fabrication is simpler, but storage density is limited
Solution Approach 1:
The patent creates a universal memory cell structure where the same basic building block (cross-point memory cell with bit line, word line, and charge storage structure) can be replicated and stacked multiple times to achieve different storage densities. The same fabrication process and material layers serve multiple functions - dielectric layers provide both isolation and structural support, conductive layers serve as both interconnects and memory elements. This universality simplifies manufacturing while enabling high density through repetition and stacking.
3Reliability
If multiple access lines are used for each memory cell, then processing control is improved, but power dissipation increases
Solution Approach 1:
The patent merges the access control function into a single unified structure. At each cross-point where a bit line and word line intersect, a select transistor controls access to the memory cell. This single transistor per cell approach consolidates the access control that would otherwise require multiple separate access lines, reducing the total number of conductors and associated power consumption while maintaining precise control over each memory cell's read/write operations.
Data Source
AI summary
Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.