3D 8T SRAM Bit-Cell Layout for Uniform Access Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of semiconductor integrated circuits (ICs) due to smaller geometry sizes and higher functional densities leads to performance discrepancies among SRAM bit-cells within an array, affecting access and sensing speeds, especially due to varying distances from peripheral components like sensing amplifiers and word line drivers.
Innovation Solution
Implementing a three-tier architecture with 8 transistors (8T) SRAM bit-cells, incorporating two pairs of pass-gate transistors for read-enhanced and dual-port configurations, which include additional pass-gate transistors connected to separate word lines for improved read operations and dual-port access, respectively, maintaining the same physical footprint as standard 6T bit-cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If standard 6T SRAM bit-cells are used, then the physical footprint is small, but the read and write operations are slower and performance varies across array locations
Solution Approach 1:
The patent implements a three-tier vertical architecture where pass-gate transistors are positioned in a third tier above the traditional planar structure. This vertical stacking allows additional functionality (enhanced read operations with dual ports) without increasing the lateral footprint, resolving the contradiction between improved speed and increased device complexity
Solution Approach 2:
The patent nests multiple functional layers within the same physical footprint. The 8T bit-cell structure incorporates two pairs of pass-gate transistors that are vertically integrated with the storage cells, allowing enhanced read/write operations while maintaining the same area as standard 6T cells. The additional transistors are effectively 'nested' in the vertical dimension rather than expanding horizontally
2Productivity
If functional density is increased, then more devices fit per chip area, but performance discrepancies increase due to varying distances from peripheral components
Solution Approach 1:
By moving pass-gate transistors to a third vertical tier, the patent reduces the lateral distance signals must travel to access peripheral components. The vertical stacking compresses the effective signal path, allowing high functional density while maintaining performance consistency across the array by reducing the impact of positional variations
Solution Approach 2:
The patent enhances local read operations at each bit-cell location with dedicated pass-gate transistors in the third tier, providing consistent performance characteristics across all array locations regardless of distance from peripheral sensing amplifiers or word line drivers
Data Source
AI summary
A method includes forming a first bottom-tier pull-up transistor and a second bottom-tier pull-up transistor over a substrate, wherein the first and second bottom-tier pull-up transistors are comprised in a static random access memory (SRAM) cell; forming a first middle-tier pull-down transistor and a second middle-tier pull-down transistor over the first and second bottom-tier pull-up transistors, wherein the first and second middle-tier pull-down transistors are comprised in the SRAM cell; forming a first top-tier pass-gate transistor, a second top-tier pass-gate transistor, a third top-tier pass-gate transistor, and a fourth top-tier pass-gate transistor over the first and second middle-tier pull-down transistors, wherein the first, second, third, and fourth top-tier pass-gate transistors are comprised in the SRAM cell.