3D Neural Network Accelerator Dataflow Bypass for Faulty Tiles

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Solution Overview

Problem

Three-dimensionally stacked neural network accelerators often suffer from poor yield due to the likelihood of faulty computing tiles, which can render the entire system inoperable, despite being cheaper and more compact than traditional accelerators.

Innovation Solution

Modifying the dataflow configuration to bypass faulty tiles by routing outputs to input connections on different neural network dies, enabling continued functionality and increasing the yield of operable accelerators by creating alternative data paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If more computing tiles are stacked vertically to increase processing capacity, then the accelerator becomes more compact and cost-effective, but the probability of having faulty tiles increases, rendering the entire system inoperable

Engineering Contradiction:
Improveprocessing capacityVSAvoidsystem operability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system segments the dataflow into multiple independent paths through different tiles. Instead of a single linear dataflow through all tiles, the configuration allows data to be processed through alternative sequences of tiles, creating modular redundancy where the system can function with partial tile failures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the dataflow configuration by allowing dynamic reconfiguration of data paths at different time steps. This enables the system to adaptively route data around faulty tiles by changing the processing sequence, effectively adding a time-based dimension to the spatial tile arrangement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If traditional fabrication mechanisms are used for three-dimensionally stacked accelerators, then manufacturing cost is reduced and compactness is achieved, but yield of operable accelerators deteriorates due to faulty dies

Engineering Contradiction:
Improvefabrication costVSAvoidyield of operable accelerators
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The system changes the operational parameters of the tile stack by dynamically reconfiguring which tiles are active and how data flows through them. This allows the same physical hardware to operate in multiple configurations, effectively increasing yield by allowing accelerators with some faulty tiles to still function at reduced but acceptable capacity.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If a linear dataflow configuration is used through all tiles, then processing simplicity is maintained, but a single faulty tile renders the entire accelerator inoperable

Engineering Contradiction:
Improvedataflow configurationVSAvoidfault tolerance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The dataflow configuration transitions from a static linear arrangement to a dynamic reconfigurable system. The controller can modify the dataflow configuration at runtime based on which tiles are functional, allowing the system to adapt to hardware variations and failures without requiring a complete system redesign.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11836598B2Yield improvements for three-dimensionally stacked neural network accelerators
Publication Date: 2023.12.05 GOOGLE LLC
  • US11836598B2 patent drawing
  • US11836598B2 patent drawing
  • US11836598B2 patent drawing

AI summary

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.