3D AND Flash Memory Gate Stack Transistor Integration
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Solution Overview
Problem
Current 3D AND flash memory devices face read errors due to limitations in their design and fabrication processes, which affect the accuracy and reliability of data retrieval.
Innovation Solution
A 3D AND flash memory device is designed with a gate stack structure, channel pillar, source pillar, and transistors that serve as switches, integrated into a memory array to avoid read errors. The fabrication method involves forming a stack structure on a dielectric substrate, creating channel and source/drain pillars, and forming charge storage structures between gate layers and channel pillars, with transistors connected to bit and source lines to enhance data retrieval accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are integrated into the memory array as switches, then read errors are avoided and data retrieval accuracy is improved, but device complexity and fabrication process difficulty increase
Solution Approach 1:
The patent merges the transistor switch structure directly into the memory array by integrating select lines with word lines to form combined gate structures. This integration reduces the need for separate switch components while maintaining the switching function, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The gate stack structure serves multiple functions simultaneously: it acts as both the memory cell gate for data storage and as the select switch gate for data retrieval control. This multi-functionality eliminates the need for dedicated switch transistors, improving read accuracy while controlling device complexity
2Reliability
If a gate stack structure with multiple gate layers and insulating layers is formed, then control over the channel is improved and read errors are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate control is segmented into multiple distinct layers (first gate layer, second gate layer, third gate layer) with insulating layers between them. Each layer can be independently controlled via separate select lines, allowing precise control over channel conduction and improving read reliability while managing manufacturing precision through modular layer formation
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the gate layers and channel pillar. These intermediary layers provide electrical isolation and control interfaces, enabling precise gate control for read error avoidance while standardizing the manufacturing process through defined layer deposition sequences
Data Source
AI summary
A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.