3D Antenna Package Layout for Compact Multi-Antenna Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current antenna packaging technologies face limitations in miniaturization and signal transmission due to fixed antenna lengths and spatial constraints, which hinder the integration of multiple antennas and affect signal quality in wireless communication devices.
Innovation Solution
The packaging structure incorporates antennas on both the surface and sidewall of an embedded substrate, utilizing conducting through hole columns to connect interconnecting and outer-layer circuits, allowing for extended antenna lengths and increased spatial coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If antenna layers are separately located on upper and lower surfaces of a package or package substrate, then antenna configurations can be achieved, but the antenna layer structure occupies additional area originally used for arranging rewiring layer, causing limitations to design and manufacturing processes
Solution Approach 1:
The patent transitions from two-dimensional planar antenna arrangements on package surfaces to three-dimensional antenna structures by forming antenna layers within through-hole columns that extend vertically through the package substrate. This vertical dimension allows antenna circuits to be arranged in multiple levels without occupying additional horizontal surface area, resolving the contradiction between antenna configuration versatility and package surface area utilization.
2Reliability
If antenna length is increased to meet signal transmission requirements, then signal transmission quality improves, but the thickness of package dielectric layer must increase, making it impossible for antenna package to meet miniaturization requirements
Solution Approach 1:
The patent enables long antenna circuits to be arranged within vertical through-hole columns, allowing the antenna path length to extend in the vertical dimension rather than requiring increased horizontal or dielectric thickness dimensions. This allows signal transmission quality to be maintained through longer antenna paths without increasing package dielectric layer thickness, thus meeting miniaturization requirements.
3Reliability
If more antennas are configured to meet signal quality and transmission speed requirements, then communication system operational requirements are met, but the flat antenna structure with fixed substrate dimensions results in limited wiring space and spatial coverage
Solution Approach 1:
The patent utilizes vertical through-hole columns to create multi-level antenna structures, enabling multiple antennas to be arranged in the vertical dimension within the same horizontal footprint. This three-dimensional arrangement provides sufficient wiring space and spatial coverage for multiple antennas without requiring larger substrate dimensions, maintaining device compactness while meeting signal quality and transmission speed requirements.
4Reliability
If discrete antennas are installed on circuit board, then antenna functionality is achieved, but separate manufacturing costs are incurred and high integration and miniaturization requirements cannot be met
Solution Approach 1:
The patent merges the antenna structure with the package substrate by forming antenna layers within through-hole columns of the package itself, rather than using separate discrete antennas mounted on the circuit board. This integration combines the package substrate and antenna into a single unified structure, achieving antenna functionality while reducing manufacturing complexity and enabling miniaturization through the elimination of separate antenna components and their associated assembly processes.
Data Source
AI summary
A packaging structure with an antenna and a manufacturing method thereof are disclosed. The packaging structure includes a package, an antenna circuit, an interconnecting circuit, an outer-layer circuit, and a chip. The package is internally packaged with a first conducting through hole column and a second conducting through hole column. The antenna circuit is disposed on a first surface and a sidewall of the package. The interconnecting circuit is packaged in the package, and is connected to the antenna circuit by the first conducting through hole column. The outer-layer circuit is disposed on a second surface of the package, and is connected to the interconnecting circuit by the second conducting through hole column. The outer-layer circuit is further connected to a conductive pin. The chip is packaged in the package, and is connected to the interconnecting circuit or the outer-layer circuit.