3D Antifuse Structure for Lower Breakdown Voltage
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Solution Overview
Problem
Antifuses in semiconductor devices occupy a large area, which is a challenge as semiconductor devices become more highly integrated, requiring smaller and more efficient fault tolerance solutions.
Innovation Solution
A fuse component with a three-dimensional (3D) structure is developed, featuring a fuse dielectric layer extending into an active region and a gate metal layer surrounded by the dielectric layer, allowing for a reduced footprint and increased overlapping perimeter without occupying additional space, thereby reducing breakdown voltage and enhancing the probability of successful fusing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional planar antifuse structure is used, then the breakdown conditions are favorable, but the area footprint is large
Solution Approach 1:
The patent transitions from a two-dimensional planar antifuse structure to a three-dimensional structure by forming a trench in the substrate and placing the dielectric layer and electrode within the trench. This vertical dimensionality change allows the same functional performance in a smaller footprint area, directly resolving the contradiction between area reduction and maintaining reliable breakdown conditions
2Reliability
If the overlapping perimeter between active region and gate metal layer is increased, then the breakdown voltage is reduced, but the area occupied increases
Solution Approach 1:
By forming the electrode within a trench and surrounding it with dielectric material that extends into the active region, the patent creates a three-dimensional overlapping configuration. This allows the overlapping perimeter to be increased through vertical and lateral extension within the trench structure without proportionally increasing the surface footprint, thus reducing breakdown voltage while occupying minimal area
3Productivity
If semiconductor devices are highly integrated, then the device density is increased, but the area available for antifuses is reduced
Solution Approach 1:
The trench-based three-dimensional structure allows antifuses to be formed with significantly reduced footprint compared to planar structures. This enables higher device density by accommodating more antifuses per unit area, directly supporting highly integrated semiconductor devices while maintaining the necessary antifuse functionality
Solution Approach 2:
The patent nests the electrode within the dielectric layer, which is in turn nested within the trench structure formed in the substrate. This nested configuration maximizes the use of available space within the vertical dimension, allowing compact integration of multiple components in a small footprint area, thereby enabling higher device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D structure of the fuse component significantly reduces area consumption and increases the overlapping perimeter between the active region and the gate metal layer, leading to lower breakdown voltage and higher success rates in fusing operations.
Implementation Method 1
The gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region
Data Source
AI summary
A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.