3D Anti-Fuse Memory Cell Layout for Faster Readout
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Solution Overview
Problem
Existing memory devices face challenges in achieving compact chip design and robust performance due to limitations in reducing area and increasing reading speed.
Innovation Solution
The proposed memory device incorporates a plurality of anti-fuse memory cells, each comprising a programming transistor and at least one reading transistor, configured in various combinations of 2D and 3D transistors. These memory cells are stacked relative to peripheral transistors and bit lines, optimizing spatial arrangements to reduce area and enhance reading speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory devices use conventional 2D transistor arrangements, then manufacturing is simpler, but chip area is larger and reading speed is slower
Solution Approach 1:
The patent transitions from conventional 2D transistor arrangements to 3D stacked transistor configurations. Memory cells are arranged in multiple vertical layers with select lines extending through multiple layers, enabling three-dimensional spatial utilization. This dimensional change increases storage density and reading speed while managing chip area effectively.
Solution Approach 2:
The patent implements nested structures where memory cells are stacked vertically within the same planar footprint. Multiple memory cell layers are positioned one above another, with shared select lines penetrating through multiple layers. This nesting approach maximizes space utilization and improves reading speed without proportionally increasing chip area.
2Area of stationary object
If memory devices increase storage density through compact arrangements, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory structure into discrete stacked layers, with each layer containing memory cells and select lines. This segmentation allows for modular manufacturing where each layer can be formed and aligned systematically. The segmented approach to 3D stacking enables precise positioning while maintaining manufacturing feasibility through step-by-step layer formation.
Solution Approach 2:
The patent employs parameter changes in the vertical dimension, stacking memory cells at different heights and positions along the vertical axis. By utilizing the Z-dimension for cell placement rather than only planar X-Y positioning, the system achieves higher density without proportionally increasing manufacturing precision demands in the lateral directions.
3Productivity
If memory devices use 3D stacked configurations, then reading speed and density improve, but device complexity increases
Solution Approach 1:
The patent implements universal select lines that extend through multiple memory cell layers, serving multiple functions simultaneously. A single select line can activate memory cells across different vertical layers, reducing the total number of select lines needed compared to fully independent layer control. This multi-functionality simplifies the overall device complexity while maintaining high reading speed through parallel access capability.
Solution Approach 2:
The patent merges multiple memory cell layers into a unified 3D structure with shared select lines and word lines. By combining layers vertically rather than keeping them as separate planar structures, the patent achieves higher density and reading speed while reducing the total component count. The merged structure allows simultaneous operation across layers, improving productivity without linearly increasing complexity.
Data Source
AI summary
A memory device includes peripheral transistors formed along a first surface of a substate; memory cells formed in one or more of first metallization layers disposed over the first surface, each of the memory cells being operatively coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and second metallization layers disposed over a second surface of the substrate opposite to the first surface. A first source/drain terminal of the first reading transistor is in electrical connection with a first source/drain terminal of the programming transistor. A second source/drain terminal of the first reading transistor is in electrical connection with a bit line that is formed in a corresponding one of the second metallization layers.