3D Arithmetic-Memory Block Layout for Faster Low-Power AI Computing

Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high performance while minimizing area occupancy, power consumption, and improving arithmetic processing speed.

Innovation Solution

The semiconductor device incorporates a plurality of arithmetic blocks with an arithmetic circuit portion and a memory circuit portion, where the arithmetic circuit portion and memory circuit portion have an overlap region, and are connected by driver circuits, utilizing silicon transistors and oxide semiconductors to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If an SoC technology is applied to improve performance, then processing speed is improved, but heat generation and power consumption increase

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements a three-dimensional stacked architecture where memory circuit portions are positioned directly over arithmetic circuit portions, utilizing vertical stacking to reduce horizontal area and improve spatial efficiency. This dimensional transition from planar to vertical arrangement enables closer proximity between compute and storage units, reducing data transfer distances and energy consumption.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds memory circuit portions within the vertical space above arithmetic circuit portions, creating a nested configuration where storage units are positioned within the footprint of compute units. This nesting approach allows memory and arithmetic circuits to share the same horizontal area, reducing overall device area and improving integration density.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Speed

If an SoC technology is applied to improve performance, then processing speed is improved, but area occupancy increases

Engineering Contradiction:

Improveprocessing speedVSAvoidarea occupancy

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent implements a three-dimensional stacked architecture where memory circuit portions are positioned directly over arithmetic circuit portions, utilizing vertical stacking to reduce horizontal area and improve spatial efficiency. This dimensional transition from planar to vertical arrangement enables closer proximity between compute and storage units, reducing data transfer distances and energy consumption.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds memory circuit portions within the vertical space above arithmetic circuit portions, creating a nested configuration where storage units are positioned within the footprint of compute units. This nesting approach allows memory and arithmetic circuits to share the same horizontal area, reducing overall device area and improving integration density.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Productivity

If AI technology with large amount of calculation is used, then computational capability is improved, but heat generation increases

Engineering Contradiction:

Improvecomputational capabilityVSAvoidheat generation

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The patent implements a three-dimensional stacked architecture where memory circuit portions are positioned directly over arithmetic circuit portions, utilizing vertical stacking to reduce horizontal area and improve spatial efficiency. This dimensional transition from planar to vertical arrangement enables closer proximity between compute and storage units, reducing data transfer distances and energy consumption.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges arithmetic circuit portions and memory circuit portions into tightly coupled arithmetic blocks, where compute and storage functions are integrated within the same vertical column. This merging reduces the distance between data processing and storage operations, minimizing data transfer overhead and associated heat generation while improving computational efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12211584B2Semiconductor device

Publication Date: 2025.01.28 SEMICON ENERGY LAB CO LTD

AI summary

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.