3D ASIC Security via Segmented Sub-circuit Stacking
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Solution Overview
Problem
The Department of Defense faces challenges in obtaining trusted Application Specific Integrated Circuits (ASICs) due to the risk of malicious or damaging features being inserted during fabrication, especially when circuit designs are sent to low-cost countries with unsecured facilities, and the cost of domestic secure fabrication is prohibitive.
Innovation Solution
The method involves fabricating multiple sub-circuits with rotational symmetry and compass orientation points, which are assembled into a 3D ASIC device in a trusted facility, allowing secure integration without revealing the overall design, enabling secure and trusted ASICs to be produced even in untrusted facilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If circuit designs are sent to low-cost countries for fabrication, then manufacturing cost is reduced, but security and trustworthiness of the ASICs deteriorate due to risk of malicious features being inserted
Solution Approach 1:
The ASIC design is divided into multiple sub-circuits that are fabricated separately in untrusted facilities. Each sub-circuit appears functional but is incomplete without the others. The segmentation prevents any single fabrication facility from obtaining the complete design, thereby maintaining security while allowing distributed manufacturing.
Solution Approach 2:
The patent transitions from traditional 2D planar integration to 3D vertical stacking of sub-circuits. This dimensional change enables the assembly of multiple independently fabricated sub-circuits into a functional whole only in the third dimension, creating security through the complexity of 3D integration while maintaining cost benefits of distributed fabrication.
2Reliability
If complete ASIC design is kept in trusted facilities, then security is improved, but manufacturing cost and productivity deteriorate due to prohibitive costs of domestic secure fabrication
Solution Approach 1:
The design is segmented into sub-circuits that can be fabricated in multiple untrusted facilities simultaneously, parallelizing the manufacturing process. This segmentation enables cost-effective distributed production while the trusted facility retains control over the integration process, achieving both security and productivity.
Solution Approach 2:
The patent introduces an intermediary integration layer that receives independently fabricated sub-circuits and assembles them into the complete ASIC. This intermediary trusted facility performs only the integration function, minimizing its workload and cost while maintaining security control over the final assembly process.
3Reliability
If ASIC fabrication is centralized in domestic secure facilities, then trustworthiness is improved, but manufacturing cost increases and supply availability decreases
Solution Approach 1:
The fabrication process is segmented into multiple independent sub-circuit fabrication steps that can be performed in untrusted facilities, followed by centralized trusted integration. This segmentation enables widespread distributed fabrication while maintaining final trustworthiness through controlled assembly, improving supply availability without sacrificing security.
Solution Approach 2:
The patent uses 3D vertical stacking to integrate sub-circuits fabricated in different locations, enabling centralized trusted integration without requiring centralized fabrication. This dimensional approach allows multiple geographically distributed fabrication facilities to contribute to a single secure final product, improving supply availability while maintaining trustworthiness.
4Ease of operation
If sub-circuits are made rotationally symmetrical with orientation points, then ease of assembly is improved, but device complexity increases
Solution Approach 1:
While the overall sub-circuit layout appears rotationally symmetrical, each sub-circuit contains asymmetric orientation points and asymmetric internal connectivity patterns. This controlled asymmetry enables automatic orientation during assembly while maintaining the visual symmetry needed for ease of placement, resolving the contradiction between ease of assembly and structural complexity.
Data Source
AI summary
A system and a method for providing secure and trusted application specific integrated circuits (ASICs) using three-dimensional (3D) integrated circuit (IC) integration. The method includes fabricating a plurality of sub-circuits and assembling an overall 3D ASIC device from the plurality of sub-circuits. Each sub-circuit includes a plurality of input-output (IO) pads, is fabricated with a orientation point that indicates a compass orientation of the sub-circuit, and is rotationally symmetrical. The assembling includes determining the designed sub-circuit integration order, determining the designed orientation for each sub-circuit, stacking each sub-circuit per the determined integration order, and orienting each sub-circuit per the determined orientation, and wherein function and operation of the overall 3D ASIC device is determinable only from the assembled 3D ASIC stack and not the sub-circuits. The fabricating may be performed at one or more un-trusted facilities and the assembling may be performed at a trusted facility remote from the fabricating facilities.