3D Semiconductor Assembly Hybrid Bonding Without CMP Surface Loss
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DICs) face challenges in reducing bonding failure risk during semiconductor assembly, particularly due to issues with bonding quality and surface area degradation caused by chemical-mechanical planarization processes.
Innovation Solution
The semiconductor assembly involves stacking semiconductor elements with wells of different doping types, ensuring a sufficient bonding surface area by controlling the height of conductive vias without using chemical-mechanical planarization, and employing hybrid bonding techniques such as metal-to-metal and non-metal-to-non-metal bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical planarization is used to prepare bonding surfaces, then surface flatness is improved, but bonding surface area is reduced due to rounding corners and sloping edges
Solution Approach 1:
The patent removes the chemical-mechanical planarization step from the bonding preparation process. Instead of using CMP to flatten surfaces, the invention directly bonds surfaces that have been prepared by other means (such as mechanical polishing or etching), thereby eliminating the harmful effect of CMP-induced surface area reduction while maintaining adequate surface flatness for bonding.
Solution Approach 2:
The patent performs preliminary surface preparation through alternative methods (mechanical polishing, etching, or abrasive blasting) before bonding, rather than relying on CMP immediately before bonding. This preliminary preparation achieves sufficient flatness without the detrimental rounding and sloping effects that would reduce bonding area.
2Adaptability or versatility
If multiple semiconductor chips are stacked to increase functional integration, then device functionality is improved, but bonding failure risk increases
Solution Approach 1:
The patent employs preliminary surface preparation steps (mechanical polishing, etching, or abrasive blasting) that create surfaces with adequate flatness and bonding area before the actual bonding process. This cushioning approach ensures that subsequent bonding operations have a robust foundation, reducing the risk of bonding failures in stacked chip configurations.
Solution Approach 2:
The patent changes the surface preparation parameters by eliminating CMP and using alternative methods with different surface morphology characteristics. This parameter change maintains or improves bonding surface area while achieving sufficient flatness, thereby reducing bonding failure risk in multi-chip stacks.
3Strength
If bonding surface area is increased to improve bonding quality, then bonding strength is improved, but manufacturing complexity increases
Solution Approach 1:
The patent removes the CMP process step to prevent surface area reduction. By eliminating this complex manufacturing step, the invention maintains larger bonding surfaces and improves bonding strength while actually reducing manufacturing complexity compared to processes that require CMP.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bonding quality and reduces the risk of failure by maintaining a larger bonding surface area and preventing rounding corners or sloping edges, thereby improving the reliability of the semiconductor assembly.
Implementation Method 1
bonding the first conductive via to the second conductive via
Implementation Method 2
the first well overlaps with the second well in a longitudinal direction after the first conductive via is bonded to the second conductive via
Data Source
AI summary
A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.