3D Backside Illuminated Image Sensor Multiplexed Pixel Structure
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Solution Overview
Problem
Conventional two-dimensional front-side-illuminated image sensors face limitations in pixel multiplexing due to optical interference and space constraints, restricting the number of pixels that can be multiplexed without compromising optical symmetry and photocollection efficiency.
Innovation Solution
A three-dimensional backside illuminated image sensor structure positions photodiodes above transfer gate lines, relocating interconnect metallization out of the optical path, allowing for increased pixel multiplexing without disturbing optical symmetry and reducing transistor density, enabling more efficient photocollection and additional circuitry integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If interconnect metallization is positioned in the optical path (conventional front-side-illuminated structure), then routing is simplified, but optical interference occurs and photocollection efficiency deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure. The photodiode layer is positioned above the transfer gate lines in the vertical dimension, moving interconnect metallization out of the optical path. This dimensional change allows light to reach photodiodes without passing through metal interconnects, eliminating optical interference while maintaining routing capabilities through vertical stacking.
2Device complexity
If pixel multiplexing is increased in conventional two-dimensional structures, then transistor density is reduced, but optical symmetry is disturbed and photocollection efficiency decreases
Solution Approach 1:
By stacking photodiodes above transfer gates in the vertical dimension, the patent enables higher pixel multiplexing (e.g., 4x4 or 16x4 multiplexing) without disturbing optical symmetry. The three-dimensional arrangement separates optical paths from interconnect routing, allowing multiple pixels to share transistors while maintaining uniform light collection across all pixels.
3Adaptability or versatility
If more transistors are integrated per pixel (4T structure), then pixel functionality is improved, but pixel area increases
Solution Approach 1:
The patent implements pixel multiplexing where multiple pixels share common transistors (reset transistor, source follower transistor, row select transistor). For example, in a 4x4 multiplexed array, 16 pixels share 16 transistors, reducing the average transistor count per pixel from 4 to 1. This merging approach maintains full pixel functionality while significantly reducing the area required per pixel.
Solution Approach 2:
The three-dimensional stacking allows complex transistor circuits to be positioned below the photodiode layer in the vertical dimension, freeing up horizontal pixel area. The photodiode layer sits above the interconnect metallization and transistor layer, enabling high functionality without increasing lateral pixel footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances photocollection efficiency, reduces transistor density, and allows for higher levels of pixel multiplexing, such as 4-way or 16-way, without optical interference, thereby improving image sensor performance and reducing the complexity of interconnect routing.
Implementation Method 1
Each pixel includes at least a photosensitive element for providing a signal having a magnitude proportional to the intensity of light incident on the photosensitive element
Data Source
AI summary
A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array includes multiple groups of pixels, each group of pixels including a first layer and a second layer. The first layer includes multiple photosensitive elements, one per pixel in the group, at least one floating diffusion region connected to each photosensitive element in the group via at least one respective transfer gate per pixel and multiple transfer gate lines, at least two transfer gate lines connected to each respective transfer gate in each row of pixels. The second layer includes at least a rest transistor per group and a source follower transistor coupled to the shared floating diffusion in the first layer.