3D Stacked Base-Die Redundancy Using Cross-Chip Block Bridges
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Solution Overview
Problem
In 3D stacked devices, certain blocks must be functional in the bottommost chip, but if a defect occurs in a fabric region connected to these blocks, the corresponding portion of the device becomes unreachable and unusable, lacking redundancy.
Innovation Solution
The 3D stacked device is configured with a redundant logical layer by dividing semiconductor chips into slivers and sub-slivers, where each block is coupled through inter-block bridges, allowing data to be routed from an active first block to an active second block, even if the latter is in a different semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blocks are replicated in upper layers of 3D stacked device, then redundancy is provided for most blocks, but blocks that must be functional in bottommost chip (I/O blocks, GT blocks, PS blocks) cannot use upper layer counterparts for redundancy
Solution Approach 1:
The device is divided into multiple slivers, where each sliver contains blocks from different layers including both base layer blocks (I/O, GT, PS) and upper layer blocks. This segmentation allows selective activation of blocks within each sliver, enabling redundancy for base layer blocks while maintaining adaptability.
Solution Approach 2:
The patent transitions from traditional vertical layer-based organization to a three-dimensional organization using slivers that extend across multiple layers. This dimensional change allows blocks to be grouped by functional relationships rather than physical layer positions, enabling cross-layer redundancy paths.
2Reliability
If fabric region connecting to I/O or GT block in bottommost chip is defective, then the I/O or GT block becomes unreachable and unusable, rendering the block and corresponding portion of device unusable
Solution Approach 1:
Upper layer blocks act as intermediaries that can receive data from base layer I/O or GT blocks through functional fabric regions in upper layers, then relay the data to appropriate destinations. This intermediary mechanism bypasses defective fabric regions in the base layer.
Solution Approach 2:
The device is configured with redundant block arrangements and multiple potential data paths before defects occur. When a fabric region defect is detected, the system can switch to pre-configured alternative paths through upper layer blocks, cushioning against the harmful effect of the defect.
3Reliability
If blocks are organized strictly by layer with base layer blocks requiring functionality, then manufacturing simplicity is maintained, but redundancy cannot be achieved for base layer specific blocks
Solution Approach 1:
Upper layer blocks are designed to serve dual purposes: they function as normal computational blocks within their own layer and simultaneously serve as redundant alternatives for base layer blocks. This multi-functionality provides redundancy without requiring duplicate base layer blocks.
Solution Approach 2:
The patent merges the functionality of base layer blocks with upper layer blocks by grouping them together in slivers. This combining allows the system to treat blocks from different layers as a unified functional group, enabling redundancy while simplifying the overall control structure.
Data Source
AI summary
A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.


